FPGA-based LoongArch Five-stage Pipeline CPU

Abstract

We designed and implemented a five-stage pipeline CPU based on the FPGA platform, programmed in Verilog hardware description language to implement LoongArch architecture. The design and implementation of the Instruction Fetch (IF) stage, Instruction Decode (ID) stage, Instruction Execute (EX) stage, Memory Access (MEM) stage, and Write Back (WB) stage. The design and implementation of the important modules in the pipeline are given. The use of the Bubble method and Bypass technique solves most of the parameter passing problems and branch judgment problems in the pipeline. The access memory problem is solved using design tricks. Finally, the design is verified on an FPGA platform. The CPU design can be well used in learning and research related to pipeline CPUs. It can also support experimental platforms and provide an example for further research in pipelines and SOCs.