Resolving Control Hazard by Reconstituting Processor's Pipeline Organization

Abstract

Control hazard is caused because the Instruction Fetch (IF) stage fetches the next instruction before the Instruction Decode (ID) stage can evaluate the branch condition. In the proposed design, IF stage consumes the first clock cycle in fetching the new instruction and then forwards the same instruction to the consecutive ID stage at the beginning of second clock cycle. In the case of branch instruction entering the ID stage, its outcome will only be available at the end of second clock cycle. Meanwhile, the IF stage will also be ready with the next fetched instruction. At this instant, a multiplexer is used to choose between both of these instructions from IF and ID stages. The output of this multiplexer is forwarded to the Program Counter (PC) register that will eventually result in resolving the control hazard without causing any stall. In addition, to prove the effectiveness of the proposed design, we have compared its outcome with the outcomes of the other existing architectures, such as Intel(R) core(TM) i3, i5 and i7 processors. We have used the Intel(R) VTune Amplifier 2018 software for studying the branch mispredictions and gathering the respective data.