Novel and Prevalent Techniques for Resolving Control Hazard

Abstract

AbstractIn a standard pipelined RISC processor, the succeeding instruction in the program enters the instruction fetch (IF) stage before the branch condition is evaluated in the instruction decode (ID) stage. A wrong instruction may enter the processer in this hustle, causing control hazard. Earlier in single-core processors, techniques of static and dynamic branch predictions were used to predict the branch for fetching the correct instructions. Later, the processor technology enhanced and brought multithreading and multicore techniques into play. Current study analyzes the novel and prevalent techniques, such as reconstituting processor’s pipeline organization, speculative execution using multithreading, and fine-grained multithreading, for resolving the control hazard.KeywordsControl hazardBranch predictionSpeculative multithreadingFine-grain multithreadingOut of order executionThread-level parallelism