Improving Energy Efficiency through Parallelization and Vectorization on Intel Core i5 and i7 Processors

Abstract

Driven by the utilization wall and the Dark Silicon effect, energy efficiency has become a key research area in microprocessor design. Vectorization, parallelization, specialization and heterogeneity are the key design points to deal with the utilization wall. Heterogeneous architectures are enhanced with architectural optimizations, such as vectorization, to further increase the energy efficiency of the processor, reducing the number of instructions that go through the pipeline and leveraging the usage of the memory hierarchy. AMD <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> Fusion <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> or Intel Core i5 and i7 are commercial examples of this new generation of microprocessors. Still, there is a question to be answered: How can software developers maximize energy efficiency of these architectures? In this paper, we evaluate the energy efficiency of different processors from the Intel Core i5 and i7 family, using selected benchmarks from the PARSEC suite with variable core counts and vectorization techniques to quantify energy efficiency under the Thermal Design Power (TDP). Results show that software developers should prioritize vectorization over parallelization whenever possible, as it is much better in terms of energy efficiency. When using vectorization and parallelization simultaneously, scalability of the application can be reduced drastically, and may require different development strategies to maximize resource utilization in order to increase energy efficiency. This is especially true in the server market, where we can find more than one processor per board. Finally, when comparing on-chip and “at the wall” energy savings, we can see variations from 5 to 20%, depending on the benchmark and system. This high variability shows the need to develop a more detailed model to predict system power based on on-chip power information.