Multi-zero pole dynamically compensated LDO with low quiescent current

Abstract

This paper presents an LDO design tailored to the various power domains of CPUs. In contemporary CPU designs, different functional modules typically necessitate distinct voltage levels, thus requiring a flexible and adjustable power management approach. An LDO with an internally compensated super source follower (SSF) and a multi-zero-pole compensated loop stability is proposed. The SSF is used to reduce the output impedance of the LDO, enhancing its carry-under-load capability. The loop is then transformed into a multi-zero-pole system through Miller compensation, feed-forward compensation, and zero-pole tracking compensation techniques, enabling the LDO to achieve stability and reliability under different loads. The LDO proposed in this study was designed using a 110 nm CMOS process. The LDO can operate within a temperature range of −40–150 °C, with a low quiescent current of 57 μA. The power supply rejection ratio of the circuit is −22 dB at 1 MHz. When the load current jumps from 5 mA to 300 mA within 40 μs, the output voltage experiences an undershoot of 271 mV, an overshoot of 174 mV, and a maximum adjustment time of 100 μs. The load regulation is 0.00267 mV/mA, and the line regulation is 1 mV/V.