CPU Design Research Articles

Design of a 16-bit Non-pipelined RISC CPU in a Two Phase Drive Adiabatic Dynamic CMOS Logic

We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an instruction decoder unit, a multiplexer and a clock control unit. Through the SPICE simulation, the 2PADCL CPU was evaluated for 0.35μm standard CMOS library and was compared with the CMOS CPU. The simulation results show that the power consumption of the adiabatic CPU is about 1/4 compared to that of the CMOS CPU.

Using DLSim 3

Students of Computer Organization should be able to "learn by doing" at all levels of computer design. DLSim 3 is a multilevel simulation system that provides a unified platform for studying system structure, from low level combinational and sequential circuits, through design of a complete CPU. Using DLSim 3, students recognize the uniformity of system structure, as well as the principles of abstraction that link the various levels of design.

TILTS: A Fast Architectural-Level Transient Thermal Simulation Method

As power density of microprocessors is increasing rapidly and resulting in high temperatures, the reliability of chips is greatly affected, making thermal simulation a necessity for CPU designs. Current thermal simulation methods (for example, the HotSpot simulator) are very useful, but are still inefficient when performing thermal analysis for long simulation times. In this paper, we propose a novel transient thermal simulation method for CPU chips at the architecture level, TILTS(Time Invariant Linear Thermal System), which utilizes the fact that the input power trace is discretized over a fixed sampling interval to accelerate thermal simulations. TILTSallows us to calculate transient temperatures on a chip over long simulation times. Based on a linear system formulation, TILTShas the same accuracy as that of traditional thermal simulation tools and is orders of magnitude faster than previous algorithms. Compared to the HotSpot simulator, TILTS achieves speedups of 1300 for the processors in our experiments for an appropriate sampling interval of 100 s. With some additional memory space, the improved algorithm CONTILTS(Convolutional TILTS ) is about 6000 times faster than the HotSpot simulator for the processors in our experiments.

Efficiently exploring architectural design spaces via predictive modeling

Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size design spaces with many interacting parameters remains an open problem: the sheer number of experiments renders detailed simulation intractable. We attack this problem via an automated approach that builds accurate, confident predictive design-space models. We simulate sampled points, using the results to teach our models the function describing relationships among design parameters. The models produce highly accurate performance estimates for other points in the space, can be queried to predict performance impacts of architectural changes, and are very fast compared to simulation, enabling efficient discovery of tradeoffs among parameters in different regions. We validate our approach via sensitivity studies on memory hierarchy and CPU design spaces: our models generally predict IPC with only 1-2% error and reduce required simulation by two orders of magnitude. We also show the efficacy of our technique for exploring chip multiprocessor (CMP) design spaces: when trained on a 1% sample drawn from a CMP design space with 250K points and up to 55x performance swings among different system configurations, our models predict performance with only 4-5% error on average. Our approach combines with techniques to reduce time per simulation, achieving net time savings of three-four orders of magnitude.

Efficiently exploring architectural design spaces via predictive modeling

Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size design spaces with many interacting parameters remains an open problem: the sheer number of experiments renders detailed simulation intractable. We attack this problem via an automated approach that builds accurate, confident predictive design-space models. We simulate sampled points, using the results to teach our models the function describing relationships among design parameters. The models produce highly accurate performance estimates for other points in the space, can be queried to predict performance impacts of architectural changes, and are very fast compared to simulation, enabling efficient discovery of tradeoffs among parameters in different regions. We validate our approach via sensitivity studies on memory hierarchy and CPU design spaces: our models generally predict IPC with only 1-2% error and reduce required simulation by two orders of magnitude. We also show the efficacy of our technique for exploring chip multiprocessor (CMP) design spaces: when trained on a 1% sample drawn from a CMP design space with 250K points and up to 55x performance swings among different system configurations, our models predict performance with only 4-5% error on average. Our approach combines with techniques to reduce time per simulation, achieving net time savings of three-four orders of magnitude.

Efficiently exploring architectural design spaces via predictive modeling

Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size design spaces with many interacting parameters remains an open problem: the sheer number of experiments renders detailed simulation intractable. We attack this problem via an automated approach that builds accurate, confident predictive design-space models. We simulate sampled points, using the results to teach our models the function describing relationships among design parameters. The models produce highly accurate performance estimates for other points in the space, can be queried to predict performance impacts of architectural changes, and are very fast compared to simulation, enabling efficient discovery of tradeoffs among parameters in different regions. We validate our approach via sensitivity studies on memory hierarchy and CPU design spaces: our models generally predict IPC with only 1-2% error and reduce required simulation by two orders of magnitude. We also show the efficacy of our technique for exploring chip multiprocessor (CMP) design spaces: when trained on a 1% sample drawn from a CMP design space with 250K points and up to 55x performance swings among different system configurations, our models predict performance with only 4-5% error on average. Our approach combines with techniques to reduce time per simulation, achieving net time savings of three-four orders of magnitude.

Instructional Tools for Designing and Analysing a Very Simple CPU

The Very Simple CPU is an instructional aid developed to introduce students to the process of designing a microprocessor. It allows students to focus on design principles without becoming overwhelmed with complex design specifications. This paper describes the CPU and two tools used to teach students about CPU design, VHDL implementations and a Java-based simulator.

CPU design: answers to frequently asked questions

CPU design: answers to frequently asked questions

Orthogonal parallel processing in vector Pascal

Despite the widespread adoption of parallel operations in contemporary CPU designs, their use has been restricted by a lack of appropriate programming language abstractions and development environments. To fully exploit the SIMD model of computation such operations offer, programmers depend on CPU specific machine code or implementation-dependent libraries. Here we present vector Pascal (VP), a language designed to enable the elegant and efficient expression of SIMD algorithms. VP imports into Pascal abstraction mechanisms derived from functional languages, in turn having their origins in APL. In particular, it extends all operators to work on vectors of data. The type system is also extended to handle pixels and dimensional analysis. Code generation is via the ILCG system that allows retargeting to multiple different SIMD instruction sets based on formalised descriptions of the instruction set semantics.

Integrated analysis of power and performance for pipelined microprocessors

Choosing the pipeline depth of a microprocessor is one of the most critical design decisions that an architect must make in the concept phase of a microprocessor design. To be successful in today's cost/performance marketplace, modern CPU designs must effectively balance both performance and power dissipation. The choice of pipeline depth and target clock frequency has a critical impact on both of these metrics. We describe an optimization methodology based on both analytical models and detailed simulations for power and performance as a function of pipeline depth. Our results for a set of SPEC2000 applications show that, when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of our energy models. Finally, we discuss the potential risks in design quality for overly aggressive or conservative choices of pipeline depth.

Designing a NICE processor

The following article is a tutorial on CPU design aspects like instruction set design, etc. It covers in detail the design process which led to the NICE-processor (NICE is charmingly elegant), developed in 1997 (B. Ulmann, Computer Architecture News, October 1997). This architecture is very well suited for educational purposes in computer architecture since it employs a simple but very powerful orthogonal instruction set in conjunction with a true general purpose register set and versatile addressing modes. These features simplify the programming of NICE as well as its possible implementation in hardware.

Ab initio Methods for the Study of Molecular Systems for Nanometer Technology: Toward the First‐Principles Design of Molecular Computers

ABSTRACT: A top‐priority objective in the area of nanoelectronics is the design of logical circuits using single molecules so that the feature size of present computers can be dramatically reduced by several orders of magnitude, thus allowing an enormous increase in speed and leading us toward the design of a molecular CPU. Achieving this goal clearly requires a good understanding of the factors that determine single interactions between unitary molecules, as well as the means to predict these interactions for proposed target molecules prior to undertaking what are often lengthy and costly synthetic efforts. The use of ab initio techniques will help us to learn how structural, electronic and external factors influence the communication between molecules, and to develop computational approaches that will allow us to quantitatively predict the characteristics of molecular scale electronics device architectures.

CMOS PLL Design in a Digital Chip Environment

CMOS PLL‘s are becoming increasingly useful for clock synthesis and recovery in CPU and other digital chip designs. However, the packaging and process are defined to meet the requirements of the digital chip, not the analog portions of the PLL. The environment defined by the digital requirements includes the package, the process and the dominant noise source. Packages for complex digital chips are larger and have more complex frequency and signal integrity characteristics than smaller packages that are appropriate for dedicated analog chips. Digital CMOS processes lack the quality capacitors, resistors and possible variety of devices that may be found in a process developed specifically for analog purposes. Digital switching causes significant noise that dominates the spectrum that the circuit designer must worry about. This paper considers a typical CMOS PLL design from the digital chip design viewpoint.

Reprogrammable hardware for educational purposes

This paper presents a novel idea in teaching computer architecture by using programmable hardware. Current teaching models for computer architecture today are either mostly theory-only or implementation oriented. Theory-based architecture courses lack the feedback to show students the effects of their decisions. Implementation-oriented instruction emphasizes the implementation aspects, that is, very low-level implementation strategies, over CPU architecture and forces the usage of very limited CPU designs to reduce complexity. High cost and long manufacturing times are other problems associated with this approach. We propose to use field programmable gate arrays (FPGAs) to allow fast implementation of chip designs. This allows for a fast debug cycle, as designs can be altered and downloaded in a matter of hours. As FPGAs are pretested, only logic functionality has to be validated, reducing the time to get a workable implementation of a chip considerably.

Using transformations and verification in circuit design

We show how machine-checked verification can support an approach to circuit design based on two kinds of refinement. This approach starts with a conceptually simple (but inefficient) initial design and uses a combination of ad hoc refinement and algorithmic transformation to produce a design that is more efficient (but more complex). We present an example in which we start with a simplified CPU design and derive an efficient pipelined form, including circuitry for reverting the effects of partially executed instructions when a successful branch is detected late in the pipeline. The algorithmic stage of our derivation applies a transormation, retiming, that has been proven to preserve functional behavior in the general case. The ad hoc stage requires special justification, which we supply in the form of a machine-checked formal verification.

BiCMOS dynamic manchester carry look ahead circuit for high speed arithmetic unit VLSI

A new BiCMOS dynamic Manchester carry look ahead circuit is presented, which is free from race problems, for VLSI implementation in a high speed arithmetic unit. Using the BiCMOS dynamic Manchester carry look ahead circuit, a 16 bit full adder test circuit which has been designed based on a 2 μm BiCMOS technology, shows a more than two times improvement in speed as compared to the CMOS Manchester carry look ahead circuit. The speed advantage of the BiCMOS dynamic carry look ahead circuit is even greater in a 32 bit or 64 bit adder, which is very helpful for high speed VLSI CPU designs

Performance and the i860 microprocessor

The internal design of the i860 CPU, which exploits pipelining and parallelism more than previous microprocessors, is described. The i860 uses RISC concepts and memory-performance optimizations in several novel ways. Other innovations include simultaneous floating-point operations similar to digital signal processing, a two-instruction-per-clock mode, fast floating-point pipelines graphics instructions, and high-bandwidth registers and caches on-chip. These features make it one of the fastest single-chip processors available.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital Design of an Educational CPU

Digital Design of an Educational CPU

The MC68332 microcontroller

The total-system goals, CPU design goals, and modular design approach of the high-performance MC68332 microcontroller are described. The features of the system integration module, queued serial module, and standby RAM are summarized. The CPU and time processor modules are discussed in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A simulation tool for teaching CPU design and microprogramming concepts

Courses in computer architecture, among other things, must address issues of CPU design and microprogramming. Real environments, if even available, provide very specialized, vendor specific architecture solutions. Computer architecture for this reason is often approached without the benefit of any hands-on experience. Simulation obviously provides a means of exploring "new" architectures. However, simulation tools in the architecture area tend to be highly specialized, typically dictating CPU design and microprogramming organization. If engineering-level concerns of speed or timing considerations are not at issue, APL provides a uniquely effective base for building a general simulation tool to implement both mundane and exotic microprogrammable CPU designs. The authors have conceived and developed such an environment using APL. Both students and instructor can use the simulation toolkit to "implement" CPU designs or install an existing CPU architecture. The user can specify registers and function modules activated by bits in the microinstructions. CPU bus structures, the microprogram store, main memory and its access scheme are user-definable. An interface guides the construction of microcode. The simulation can be operated one instruction at a time, one microinstruction at time, or integral multiples of either. A student-ready version has been successfully class tested during the 1989 Spring semester.