Core Circuit Research Articles

Adaptive Active Control System of Vehicle Noise Design and Test

According to the vehicle interior low frequency noise existing, vehicle interior adaptive active noise control strategy is established based on the FXLMS algorithm, designed the core circuit module active noise controller, including the vehicle interior noise signal amplification module, a main control unit, audio power amplifier module and power module, completed development of the controller hardware, and programming the control software system; using this system, on vehicle driving conditions vice driver left ear position low frequency noise cancellation control in the steady state, the 8.5 dB (Lin) and 10.2dB (Lin) the amount of noise reduction.

Design of Automatic Air Purification Device

In daily life because of polluted air people have a headache, insomnia, allergic diseases, respiratory diseases, etc. Air Purifier is also called "air cleaner" or "air sober machine". It refers to an equipment which can adsorb, decompose or transform all kinds of air pollutions,and volatilize an anion to improve the indoor air quality. In order to achieve the purpose of the microcomputer digital control of system, air purifier is designed with a single chip to reduce the artificial control. The single chip microcomputer is regarded as the core circuit part of the whole control system, the function of which is control all components of the air purification. Air purifier equipment consists of dust sensors, anion generator unit, fan module components and 4x4 matrix keyboard. Software program mainly includes: the display program, keyboard program, the clock program. This design aims at starting subsequent circuit module automatically through real-time control of air quality, achieving the function of air purification.

Line Scan Sensor용 저면적 eFuse OTP 설계

In this paper, a small-area cell array method of reducing number of SL drivers requiring large layout areas, where the SL drivers supplying programming currents are routed in the row direction in stead of the column direction for eFuse OTP memory IPs having less number of rows than that of columns such as a cell array of four rows by eight columns, and a core circuit are proposed. By adopting the proposed cell array and core circuit, the layout area of designed 32-bit eFuse OTP memory IP is reduced. Also, a V2V (=2V±10％) regulator necessary for RWL driver and BL pull-up load to prevent non-blown eFuse from being blown from the EM phenomenon by a big current is designed. The layout size of the designed 32-bit OTP memory IP having a cell array of four rows by eight columns is 13.4% smaller with 120.1㎛ × 127.51㎛ (=0.01531㎜ 2 ) than that of the conventional design with 187.065㎛ × 94.525㎛ (=0.01768㎜ 2 ).

Overview of Dual-Active-Bridge Isolated Bidirectional DC–DC Converter for High-Frequency-Link Power-Conversion System

High-frequency-link (HFL) power conversion systems (PCSs) are attracting more and more attentions in academia and industry for high power density, reduced weight, and low noise without compromising efficiency, cost, and reliability. In HFL PCSs, dual-active-bridge (DAB) isolated bidirectional dc-dc converter (IBDC) serves as the core circuit. This paper gives an overview of DAB-IBDC for HFL PCSs. First, the research necessity and development history are introduced. Second, the research subjects about basic characterization, control strategy, soft-switching solution and variant, as well as hardware design and optimization are reviewed and analyzed. On this basis, several typical application schemes of DAB-IBDC for HPL PCSs are presented in a worldwide scope. Finally, design recommendations and future trends are presented. As the core circuit of HFL PCSs, DAB-IBDC has wide prospects. The large-scale practical application of DAB-IBDC for HFL PCSs is expected with the recent advances in solid-state semiconductors, magnetic and capacitive materials, and microelectronic technologies.

A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB

This paper presents a 12.8 GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6 ENOB in 65 nm CMOS. The prototype utilizes hierarchical sampling and cascode sampler circuits to enable greater than 25 GHz 3 dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm 2 and consumes a total of 162 mW from dual 1.2 V/1.1 V supplies. The design achieves a SNDR of 29.4 dB at low frequencies and 26.4 dB at 25 GHz, resulting in a figure-of-merit of 0.79 pJ/conversion-step. As will be further described in the paper, the circuit architecture used in this prototype enables expansion to 25.6 GS/s or 51.2 GS/s via additional interleaving without significantly impacting ERBW.

Research on the Drunk Driving Intelligent Test System Based on μC/OS-II

The article design the hardware system scheme using STM32F407 as the control core circuit, and designed the software structure of the system and application layer multi task and priority based on transplanted μC/OS operating system. Aimed at that the traditional drunk driving detection system has low sensitivity and unable to distinguish diffuse alcohol signal interference. For accurate identification of pilot and crew alcohol concentration, the paper puts forward a driving intelligent identification wine system based on embeddedμC/OS-II. The experimental results show that the detection sensitivity of the system has high accuracy rate, effectively prevent the purpose for the prevention of drunk driving, drunk driving has very good practical value.

Equivalent circuit models in current-mode circuits for time delay calculations

In this paper time delay calculations for current-mode circuits are considered and equivalent circuit models for delay estimation are developed. Three different equivalent circuit structures for the Core Circuit used in the multipurpose IC DU-TCC1209 are examined separately; however the relation obtained for the time delay can be applied to any CMOS current-mode circuit. The proposed calculation methods are verified with SPICE using 0.35 μm TSMC MOSIS technology parameters and with bench-test measurements using DU-TCC1209.

A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS

This brief presents a single-channel two-step successive approximation register (SAR) analog-to-digital converter (ADC) using a source follower as an interstage residue amplifier. An asynchronous SAR ADC with two-step timing can effectively allocate the bit-resolving procedure into the whole clock period and eliminate a dedicated duty-cycle clock generator. The arbitrary weight capacitor array technique is utilized to tolerate offset mismatch between the coarse and fine stages. The level-shift technique is used to accelerate the comparator. The ADC in 40-nm CMOS obtains 5.6 and 4.9 effective numbers of bits at Nyquist with the conversion rate of 800 MS/s and 1 GS/s, respectively. It consumes 5.3 mW at 1 GS/s and achieves a figure of merit of 180 fJ/conversion-step. The core circuit occupies an area of 0.009 $\hbox{mm}^{2}$ .

A dual‐band balanced amplifier using three‐layer technology

ABSTRACTA multilayer technology is applied to design a dual‐band branch‐line coupler for the dual‐band balanced amplifier. The proposed coupler is designed based on a three‐layer printed circuit board. The dual‐band operation is achieved by four additional shunt stubs at the middle layer, while the upper layer is the core and active circuits layer and the bottom is ground layer. The proposed coupler with equal power division is designed at two frequencies of 1.1 and 1.9 GHz. Besides, a balanced amplifier is also designed which achieves gain of 11.6 and 10.1 dB at 1.1 and 1.9 GHz, respectively. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1680–1683, 2014

Eddy Current Loss Estimation of Edge Burr-Affected Magnetic Laminations Based on Equivalent Electrical Network—Part II: Analytical Modeling and Experimental Results

In Part I of this two-part paper, fundamental concepts of interlaminar fault and its consequences on magnetic cores were presented. An equivalent configuration, which was proved by FEM modelling, was proposed for magnetic cores with interlaminar fault. In this Part II paper, based on the equivalent configuration of the core and equivalent circuit of eddy current path, an analytical model is developed to estimate eddy current power loss of magnetic cores with interlaminar faults in a wide range of magnetizing frequency. Important factors, such as skin effect, nonuniform flux density distribution, complex relative permeability and nonlinear relation of B (H), which are often neglected in the literature, are highlighted. Packs of two, three, and four Epstein-size laminations of conventional grain oriented were shorted together artificially to measure the extra power loss caused by the interlaminar fault and support the analytical modeling. It was found that in the magnetic cores affected by interlaminar fault, the skin effect is a determinant factor in the magnetic properties determinations, even at low frequencies.

Design of 5 GHz low-power CMOS LC VCO based on complementary cross-coupled topology with modified tail current-shaping technique

In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit are 2.5 mW and −188.6 dBc/Hz. The phase noise is −118 dBc/Hz@1 MHz at an operation frequency of 4.94 GHz.

Delay learning architectures for memory and classification

We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight-based ones is simpler hardware implementation without multipliers or digital–analog converters (DACs) as well as being suited to time-based computing. The name is derived due to similarity in the learning rule with an earlier architecture called tempotron. The DELTRON can remember more patterns than other delay-based networks by modifying a few delays to remember the most ‘salient’ or synchronous part of every spike pattern. We present simulations of memory capacity and classification ability of the DELTRON for different random spatio-temporal spike patterns. The memory capacity for noisy spike patterns and missing spikes is also shown. Finally, we present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture.

Design of 5‐GHz CMOS LC VCO with dual tuning circuit

ABSTRACTIn this article, a linear tuning range, low power, and low phase noise of CMOS voltage controlled oscillator (VCO) is presented. The core circuit of VCO is adopted dual‐tuning LC resonator with two transformer coupling structure. The bandwidth of the frequency range is from 4.85 to 5.84 GHz with a 18.5% tuning ratio by two tuning voltages. The phase noise of the proposed VCO is −119.3 dBc/Hz at 1 MHz offset frequency. The power consumption is 5.2 mW from 1 V supply and the KVCO exhibits the linearity with 240 MHz/V. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1356–1360, 2014

Indoor Positioning System Based on RFID

This paper presents an indoor positioning system based on RFID, which introduces electronic tag assisted positioning, according to the plurality of the electronic tags which are arranged in the target area as equilateral triangle, and the reader reads the information and Received Signal Strength Indication (RSSI) within its reading range. Sampling and calculation of the positioning result is controlled by the core circuit. Experimental results show that the indoor positioning system has excellent positioning accuracy, with high efficiency and low cost.

NanoCube: A Low-Cost, Modular, and High-Performance Embedded System for Adaptive Fabrication and Characterization of Nanogaps

This paper presents an embedded modular system, NanoCube, able to repeatedly fabricate a pair of nanometric terminal probes (nanogaps) using the electromigration-induced break junction and capable to characterize them for low-cost molecular electronic devices and biomolecular sensing. NanoCube implements a flexible control loop which predicts both temperature and current and efficiently manages the electrical stimulation applied to ad hoc PCB cartridges, including a silicon chip with gold wire probes to be electromigrated. The modular and flexible system embeds the core circuits devoted to nanogap fabrication, signal conditioning and measurement, and the microprogrammed subsystems. NanoCube runs a real-time Linux operating system, with a fully customizable electromigration algorithm which considers fabrication history to adaptively improve performance. After 250 fabrication runs the system is shown to be able to fabricate nanogaps under 3 nm with 29% yield, and with 53% yield if we consider gaps under 10 nm. To validate the system, experiments using the fabricated nanogaps with bonded oligothiophene molecules were run, verifying the theory of molecular conduction.

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation

SUMMARY A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0. 6V to 1.2 V. We fabricated the BBG in a 65 nm CMOS process to control 0. 1m m 2 of core circuit with the area overhead of 1.4%

An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe

Neural probes have become the most important tool for enabling neuroscientists to place microelectrode sensors close to individual neurons and to monitor their activity in vivo. With such devices, it is possible to perform acute or chronic extracellular recordings of electrical activity from a single neuron or from groups of neurons. After the many developments in neural implants, it has become clear that large arrays of electrodes are desirable to further investigate the activity performed by complex neural networks. Therefore, in this paper, we propose a CMOS neural probe containing 455 active electrodes in the probe shank (100 μm wide, 10 mm long, and 50 μm thick) and 52 simultaneous readout channels in the probe body (2.9 × 3.3 mm2). In situ amplification under each electrode enables low-impedance interconnection lines, regardless of the electrode impedance, with a residual crosstalk of -44.8 dB. This design has been implemented in a 0.18-μm standard CMOS technology, with additional CMOS-compatible post-processing performed at wafer level to define the electrodes and the probe outline. In this architecture, the analog front-end achieves an input-referred noise of 3.2 μVrms and an NEF of 3.08. The power consumption of the core circuit is 949.8 μW, while the total power consumption is 1.45 mW. The high-density active-electrode array in this neural probe allows for the massive recording of neural activity. In vivo measurements demonstrate successful simultaneous recordings from many individual cells.

A 38 Gb/s to 43 Gb/s Monolithic Optical Receiver in 65 nm CMOS Technology

A scaled 40 Gb/s optical receiver incorporating a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery (CDR), and a 1:4 demultiplexer was proposed in 65 nm CMOS technology. The TIA employs a regulated cascode structure to achieve low input resistance and a stable dc operating point, whereas the LA adopts the third-order interleaving active feedback technique to obtain greater bandwidth and flatter frequency response. A 10 GHz LC-based voltage controlled oscillator with a ring structure that generates eight phases is presented. A quarter-rate phase detector in the CDR samples the 40 Gb/s input data, which are retimed and demultiplexed into four sets of 10 Gb/s output data. Experimental results show that the recovered clock exhibits a phase noise of -112.39 dBc/Hz@10 MHz from a carrier frequency of 10 GHz, in response to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 PRBS input. The retimed and demultiplexed data exhibit a peak-peak jitter of 4.46 ps and an RMS jitter of 1.18 ps. The core circuit of the receiver consumes 160 mW from a 1.2 V supply.

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193dBc/Hz. The bandwidth of the frequency is 1.1GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28mW under a 1.8V supply and phase noise is measured as low as −123.6dBc/Hz at 1MHz offset under 8.5GHz oscillation frequencies. This VCO was made by the TSMC 0.18μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm2).

MicroRNA-based regulation of epithelial–hybrid–mesenchymal fate determination

Forward and backward transitions between epithelial and mesenchymal phenotypes play crucial roles in embryonic development and tissue repair. Aberrantly regulated transitions are also a hallmark of cancer metastasis. The genetic network that regulates these transitions appears to allow for the existence of a hybrid phenotype (epithelial/mesenchymal). Hybrid cells are endowed with mixed epithelial and mesenchymal characteristics, enabling specialized capabilities such as collective cell migration. Cell-fate determination between the three phenotypes is in fact regulated by a circuit composed of two highly interconnected chimeric modules--the miR-34/SNAIL and the miR-200/ZEB mutual-inhibition feedback circuits. Here, we used detailed modeling of microRNA-based regulation to study this core unit. More specifically, we investigated the functions of the two isolated modules and subsequently of the combined unit when the two modules are integrated into the full regulatory circuit. We found that miR-200/ZEB forms a tristable circuit that acts as a ternary switch, driven by miR-34/SNAIL, that is a monostable module that acts as a noise-buffering integrator of internal and external signals. We propose to associate the three stable states--(1,0), (high miR-200)/(low ZEB); (0,1), (low miR-200)/(high ZEB); and (1/2,1/2), (medium miR-200)/(medium ZEB)--with the epithelial, mesenchymal, and hybrid phenotypes, respectively. Our (1/2,1/2) state hypothesis is consistent with recent experimental studies (e.g., ZEB expression measurements in collectively migrating cells) and explains the lack of observed mesenchymal-to-hybrid transitions in metastatic cells and in induced pluripotent stem cells. Testable predictions of dynamic gene expression during complete and partial transitions are presented.