Abstract
In this paper, a small-area cell array method of reducing number of SL drivers requiring large layout areas, where the SL drivers supplying programming currents are routed in the row direction in stead of the column direction for eFuse OTP memory IPs having less number of rows than that of columns such as a cell array of four rows by eight columns, and a core circuit are proposed. By adopting the proposed cell array and core circuit, the layout area of designed 32-bit eFuse OTP memory IP is reduced. Also, a V2V (=2V±10％) regulator necessary for RWL driver and BL pull-up load to prevent non-blown eFuse from being blown from the EM phenomenon by a big current is designed. The layout size of the designed 32-bit OTP memory IP having a cell array of four rows by eight columns is 13.4% smaller with 120.1㎛ × 127.51㎛ (=0.01531㎜ 2 ) than that of the conventional design with 187.065㎛ × 94.525㎛ (=0.01768㎜ 2 ).
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