A 38 Gb/s to 43 Gb/s Monolithic Optical Receiver in 65 nm CMOS Technology

Abstract

A scaled 40 Gb/s optical receiver incorporating a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery (CDR), and a 1:4 demultiplexer was proposed in 65 nm CMOS technology. The TIA employs a regulated cascode structure to achieve low input resistance and a stable dc operating point, whereas the LA adopts the third-order interleaving active feedback technique to obtain greater bandwidth and flatter frequency response. A 10 GHz LC-based voltage controlled oscillator with a ring structure that generates eight phases is presented. A quarter-rate phase detector in the CDR samples the 40 Gb/s input data, which are retimed and demultiplexed into four sets of 10 Gb/s output data. Experimental results show that the recovered clock exhibits a phase noise of -112.39 dBc/Hz@10 MHz from a carrier frequency of 10 GHz, in response to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 PRBS input. The retimed and demultiplexed data exhibit a peak-peak jitter of 4.46 ps and an RMS jitter of 1.18 ps. The core circuit of the receiver consumes 160 mW from a 1.2 V supply.