A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS

Abstract

A fully integrated 25 Gb/s low-noise optical receiver is presented which integrates transimpedance amplifier (TIA), continuous-time linear equalizer (CTLE), high-gain and high-bandwidth limiting amplifier (LA), and clock and data recovery (CDR) circuit into a single die. The TIA employs an inverter-based pseudo-differential TIA scheme with input series-inductor peaking, cross-coupled negative Gm pair and negative capacitance to improve the bandwidth, and noise performance, while a MOSFET corner compensation (MCC) circuit compensates for CMOS corner variations. A gain control (GC) scheme is proposed which solves the group delay issue caused by TIA input impedance variations from small input to overload current. Finally, a 2x-oversampling CDR using a bang-bang phase detector is included. The receiver is fabricated in 40-nm CMOS process, and the 850 nm VCSEL-based full-link measurement results show that the optical receiver achieves 44 $\mu \text{A}_{\mathrm {pp}}$ (RSSI Current = 43 $\mu \text{A}$ , ER = 4.94 dB) optical modulation amplitude (OMA) sensitivity (BER<1e−12) with 150 fF photodiode capacitance, from 3.3-V and 1.3-V supplies, respectively.