An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit

Abstract

This paper presents an integrated optical receiver that operates at 1Gb/s in a standard 0.35μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860nm, the circuit requires an average light input power of −19.7dBm to obtain a bit-error rate (BER) of 10−12. The complete receiver consumes a total power of approximately 155mW from a 3.3-V supply. The core circuit area is 0.85×1.32mm2.