Copper Leadframe Research Articles

Thermal-Cycling-Induced Si3N4 Damage in Semiconductor Devices Assembled Utilizing a Lead-on-Chip Package

This article shows how fractures in the Si3N4 layer, which comprises the top layer of semiconductor devices encapsulated utilizing a lead-on-chip (LOC) packaging technique, are influenced by changes in the lead-frame materials and thermal-cycling test conditions. Using thermal-cycling tests, it was found that fractures in the Si 3 N 4 layer are the most sensitive to changes in the lead-frame materials at the early stage of thermal-cycling, between -65sup>oC and 150sup>oC. Through SEM examinations and stress simulations, this work shows that adopting a copper lead-frame with a CTE-value similar to that of a package body effectively prevents filler-driven Si3N4 damage, providing semiconductor devices with better reliability margins during thermal-cycling.

Investigation of through micropatterns fabrication on C194 copper foil by ultraviolet nanosecond pulsed laser microdrilling

While the lead frames of C194 copper alloy widely used in IC packages contain high density of through micropatterns, the method for realizing high precision manufacturing of the micropatterns on copper foil with thickness down to a few hundred micrometers is highly demanded. In the present work, we demonstrate the feasibility of manufacturing high density through micropatterns on C194 copper foil with high precision and high uniformity by using ultraviolet nanosecond pulsed laser microdrilling. Specifically, the absorption coefficient of C194 copper foil for 355 nm wavelength is experimentally derived, based on which the sublimation enthalpy of the material is calibrated by iteratively comparing predicted crater morphology by finite element simulations with experimental data. Then the multi-pulse laser ablation mechanisms of C194 copper foil are investigated jointly by finite element simulations and experiments, which derive the quantitative correlation of ablation crater depth with laser ablation parameters. Finally, high density arrays of through micropatterns with high dimensional accuracy and high uniformity are fabricated on C194 copper foil with a thickness of 100 μm by the proposed ultraviolet nanosecond pulsed laser microdrilling with theoretically predicted repeat scanning number. Furthermore, the effect of pickling on surface quality and resistance of the manufactured copper lead frame is addressed. This work provides a feasible method for manufacturing copper alloy lead frames with high precision through micropatterns in an environmentally friendly manner.

Sulfur Ingression on Encapsulated Leadframe of Discrete Semiconductor Package

Methanesulfonic acid (MSA) has been widely used in the electroplating step at a backend semiconductor assembly process. This process comes after component encapsulation, which serves primarily to protect internal components of a device as well as to prevent ingression of chemical byproducts. The objective of this article is to study sulfur (S) ingression activities with respect to both electroplating and encapsulation processes and their effect on leadframe surface conditions. This can be achieved through observation of leadframe surface condition on samples prepared through laser ablation or mechanical decapsulation. Results from 17 engineering lots show that 25% of samples analyzed were observed with leadframe surface irregularities. The energy-dispersive X-ray spectroscopy (EDX) analysis confirmed the trace of S element on the area with surface irregularities, which can be linked to S ingression based on the trace of its path from outside, probably due to the existence of a microgap on the package. These findings provide a clearer understanding of the ingression path of S for encapsulated copper (Cu) leadframe. Even though ingression of S does not directly cause a failure, it is thought that this could act as a precursor to further failure mechanisms such as corrosion-like phenomena.

Influence of Textured Nickel/Palladium/Gold-Silver (Ni/Pd/Au-Ag) Layer on Pre-plated Leadframe for Automotive Applications

High quality and reliability of integrated circuit packaging is required for automotive applications due to the safety concerns. Therefore, elimination and controlling the package defects which can lead to reliability failure is essential. One of the defects that leads to reliability issue is delamination. This study presents the influence of textured leadframe surfaces on the surface wettability and delamination occurrence in automotive package unit. Standard bare Cu leadframe was used as comparison. The leadframe surface was textured with Ni/Pd/Au-Ag using electroplating technique. The surface morphologies of both bare and textured leadframe were characterized using field-emission scanning electron microscope and optical profiler. The energy dispersive spectroscopy was used to quantify the elemental composition of the samples. All samples went through the wettability test under two conditions, which were room temperature and 175°C. The reliability test of complete package was subjected to moisture sensitivity preconditioning level 1 according to IPC/JEDEC STD 020 and the baking process was performed at 125°C for 24hrs followed by soaking process under the condition of 85°C and 85 of relative humidity. Scanning acoustic tomography according to IPC/JEDEC STD 035 was performed after three cycles of infrared reflow at 260°C. Higher surface roughness was observed for pre-plated leadframe (PPF) compared with bare leadframe. The lowest value of average contact angle (∼55°) was observed for PPF at 175°C indicated better wettability feature. Furthermore, no delamination occurrence was observed for PPF sample compared with bare copper leadframe. The obtained result reveals that leadframe with textured surface of Ni/Pd/Au-Ag improved interfacial surface adhesion which eliminated the delamination defect and thus improved the package robustness and reliability.

Power Semiconductor Devices and Packages: Solder Mechanical Characterization and Lifetime Prediction

Solder reliability is a key aspect for the packaging of low voltage power semiconductor device. The interconnections among package components, e.g. the silicon chip and copper leadframe, and between package itself and the external printed control board (PCB) should be properly designed to ensure the automotive durability requirements. In this framework, the proposed paper introduces an experimental-numeric characterization flow with the purpose to analyze solder visco-plasticity and fatigue during passive temperature cycle. The presented methodology has included solder mechanical characterization aimed to determine the parameters of Anand model which reproduces the solder visco-plastic behavior and the mechanical properties' temperature dependency. Finite element model has been employed to calculate the inelastic work which solder dissipates during each temperature cycle. Simulation results serve as input to predict solder lifetime according to an energetic method. Moreover, failure analyses have been performed to assess the failure mechanism and to check model correlation in terms of number of cycles to failure forecast.

Experimental and Numerical Investigation Into the Plasma Treatment and Chip Delamination in Semiconductor Packaging

Delamination between the molding compound and the die surface is a common failure pattern in the semiconductor package industry. Plasma treatment is a standard process to clean and activate the die surface to enhance the bonding force between the molding compound and the die surface in the packing procedure. However, the unexpected delamination still happens and results in a huge commercial loss for the packaged products. This study adopts experimental and numerical approaches to systematically investigate the delamination risk for plasma treatment before compound molding. A vacuum chamber is established to visualize the plasma distribution and the oxidation condition of the lead frames placed on the metal and the insulator rails. Moreover, a numerical calculation is used to systematically predict the plasma distribution over the lead frame and die surface. Results show that the lead frame placed on the metal rail exhibited a higher electric field gradient than that placed on the insulation rail. Moreover, the copper lead frame placed on the insulation rail exhibits a lower electric field gradient and less metal oxidation on the die surface. The delamination risk for semiconductor packaging can be systematically predicted and efficiently reduced before the packing process with the results obtained in the present study.

An Improvement of Plasma Cleaning Time towards Leadframe Oxidation Performance

Package delamination causing the tendency to absorb humidity which lead to device failure towards Integrated Circuit (IC) packaging[1]. Most of the screened unit being analyzed and results showed failure due to popcorn effect. Popcorn effect caused by moisture penetration effecting the packaging to expend causing delamination and cracking during high temperature application. In this paper, delamination had been filtered from Scanning Acoustic Microscope (SAM) towards the failure units and once package encapsulation had been done the root cause being identified as leadframe oxidation problem. The leadframe oxidation can be easily observed during wire bonding and oven curing process since it involved with high temperature process which the indication showed leadframe discolouration appearance. The aim of this work is to evaluate plasma parameter to achieve delamination free product by assessing the plasma cleaning time. Additional plasma cleaning before molding process had been identified as a solution towards free leadframe oxidation process which leads to zero delamination issue for package that using Copper leadframe. Higher plasma cleaning time produced significantly lower leadframe oxidation issue however the Unit Per Hour (UPH) will be effected.

Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe

We investigate the reliability of a system-in-package (SiP) technology, which uses laminate chip embedding based on a copper leadframe. For this SiP technology, we apply different Si-based transistor technologies. We test the reliability of three types of chip-embedded packages: a single-chip embedded package (SCP) with an embedded MOSFET test chip for basic understanding, and two SiPs—a multichip embedded package (MCP) with a dc/dc converter for industrial applications and a SiP for lighting applications. In order to better represent specific field stresses for the target applications, we develop and investigate new test methods for laminate-based packages. In this article, we report the design, the implementation, and the results of those new methods and discuss their benefits and validity. We conducted conventional test methods like temperature humidity bias (THB) for comparison. The results of all these tests demonstrate a very good reliability of the chip-embedded packages. We also investigate early damages inside the packages using failure analysis techniques such as cross sectioning. The cooperation of partners along the value chain resulted in a coherent understanding of chip-package-board material aspects and design for reliability.

Problemi korozije u elektronskim sistemima

Microelectronics and, chiefly, silicon integrated circuit microelectronics, has created astonishing capabilities over the last 40 years. Speedy advancement in CMOS transistor equipment leading to the gigahertz speeds common today has necessitated chief changes in semiconductor manufacturing technology and the expansion of high frequency compatible packaging. The progress of an optimized formulation for electroless nickel (EN) plating with a long life span to make a deposit with good corrosion resistance (CR). The electroless deposition of Ni-P alloys is widely used in diverse fields such as aerospace, automation, electronics, nuclear, oil and gas production, and valve industries. Lead frame is the primary package metallurgical bond pad interface in microelectronic devices which provides external interconnection. The most predominant lead frame material is copper with tin plating. Over the years, galvanic corrosion and copper oxidation are two major reliability concerns for any microelectronics packages with copper lead frame, when operating under high humidity environment.

FcLGA Package Assembly Qualification for Mobile Applications

Abstract Flip Chip Land Grid Array (FcLGA) packages are widely used in Mobile product applications due to their thin form factor and performance. Assembly process qualification requires careful selection of materials and optimization of reflow processes to make consistent and reliable product. The fcLGA typically uses an organic substrate on which the die is reflowed instead of the copper lead frame used in QFN packages. This requires assessment of CTE mismatch and controlled reflow processes to prevent bump separation [1]. The paper reviews the selection of substrate, optimization of assembly process and reliability testing conducted for package qualification

In Situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 3

In Situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 3

Aging Studies of Cu–Sn Intermetallics in Cu Micropillars Used in Flip Chip Attachment onto Cu Lead Frames

Copper micropillars plated onto a silicon die and soldered with Sn-Ag solder to a copper lead frame in a flip chip on lead package have been subjected to high-temperature storage at 150°C and 175°C for 500 h, 1000 h, and 1500 h. Cu6Sn5 and Cu3Sn intermetallic compounds were found on both sides of the solder, but the growth rates were not the same as evidenced by different values of the growth exponent n. Cu and Sn diffusion controlled the Cu3Sn growth in the Cu pillar interface (n ≈ 0.5), while interface reactions controlled the growth in the Cu lead frame interface (n ≈ 0.8). Increasing the aging temperature increased the growth of Cu3Sn as well as the presence of microvoids in the Cu lead frame side. Adding Ni as a barrier layer on the Cu pillar prevented the growth of Cu3Sn in the Cu pillar interface and reduced its growth rate on the lead frame side, even at higher aging temperatures.

Adhesion Characteristics of Epoxy Molding Compound and Copper Leadframe Interface: Impact of Environmental Reliability Stresses

Abstract Delamination at the mold compound and leadframe interface is the most common failure mode observed during processing and qualification of the microelectronic package. Mold compound to leadframe delamination is typically observed after environmental reliability stresses like: moisture preconditioning and reflow, air-to-air thermal cycling, biased highly accelerated stress etc. Leadframe based packages constitutes majority of microelectronic packages that are manufactured today, which makes mold compound/leadframe interface of great interest requiring thorough understanding of the adhesion characteristics and its evolution as a function of reliability stresses. This study used four-point bend testing to evaluate the adhesion strength of commercially available mold compound to bare copper and silver plated copper leadframes exposed to automotive grade environmental stresses. Results show that adhesion of mold compound to silver plated leadframes is significantly lower than adhesion to bare copper leadframes. Results obtained from this study can be used to carefully select the qualification reliability stresses to prevent overstressing the package and causing failures related to wire bond cracking, delamination etc., which have significant time and cost implications. Finite element simulations were also performed to validate the empirical adhesion test results and can be extended to full package level models to enable delamination prediction.

In-situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 2

In-situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction. Part 2

In-situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction.

In-situ Residual Stress Analysis of Semiconductor Packages Comprising Thermosetting Encapsulation Resins and Copper Lead Frame under Thermal Process by X-ray Diffraction.

Reliability of Heavy Gage Aluminum Wire-bonds under High Temperature Aging

Abstract Thick aluminum (Al) wedge bonds have been widely used in analog microelectronic packages due their lower cost, ease of use and excellent thermal and electrical performance. Reliability of thick Al wedge bonds on bare copper (Cu) leadframes under high temperature aging conditions has not been studied at a fundamental level in the past. This study investigates the reliability performance of Al wedge bonds on bare Cu surfaces under isothermal aging conditions specified by the automotive grade product qualification requirements. Results obtained show that Al/Cu intermetallic formed at the interface is detrimental to the mechanical and electrical package reliability. Plating on the leadframe has been evaluated as a potential mitigation to prevent intermetallic growth and hence improve the overall wedge bond and package reliability under high temperature reliability testing conditions. Significant improvement in the wedge bond and package reliability was achieved by using nickel plating under the wedge bonds. The results presented in this study can be used to design a more robust package capable of meeting stringent automotive grade requirements.

NSOP Reduction for QFN RF-IC Packages

Abstract Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – Non- stick on Pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction [1].

Experiments for Obtaining Cohesive-Zone Parameters for Copper-Mold Compound Interfacial Delamination

Interfacial delamination due to mismatch of coefficient of thermal expansion is a prominent failure mechanism of multilayer microelectronic packaging. Current methods for investigating and preventing interfacial delamination rely heavily on interfacial fracture mechanics. Such techniques are effective but also limited because they rely on assumptions about existing cracked geometry. Cohesive-zone modeling is an alternative technique for modeling interfacial delamination that is capable of simulating both crack initiation and crack propagation. This paper presents a methodology for developing a cohesive-zone model for an interface between the copper leadframe and the epoxy molding compound (EMC). Through experiments, the interfacial strength is characterized quantitatively, and load versus displacement data are collected for each experiment. By mimicking these results with a cohesive-zone model, mixed-mode cohesive-zone parameters are obtained. The fully defined mixed-mode cohesive-zone model can be used to simulate interfacial delamination between the copper leadframe and the EMC in any microelectronic package that contains such an interface. Furthermore, the procedure demonstrated here may be employed to characterize a cohesive-zone model for other interfaces in microelectronic packages.

Lifetime and manufacturability of integrated power electronics

In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially.Power electronics is a prerequisite to enable the exponential growth of power density.Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42K/W by the construction of a double side chip cooling.A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe.This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000VDC. The outlook onto an integrated 120A 700V SiC MOSFET demonstrator is given.

An in-situ numerical–experimental approach for fatigue delamination characterization in microelectronic packages

An in-situ and cost-effective numerical–experimental approach for fatigue characterization of bi-material interfaces in microelectronic packages is presented. In this method using a sample-centered approach, a miniaturized sub-critical bending (MSCB) test setup is designed and fabricated based on the samples that are acquired directly from the production-line. Sub-critical crack growth (SCCG) is captured along the surface between molding compound (MC) and copper lead-frame (LF) in the samples prepared from Thin Quad Flat Package (TQFP). The toughness values such as critical (Gc) and sub-critical strain energy release rate (Gth) are measured. It is shown that crack propagation along the MC/LF interface is highly fatigue sensitive. In addition, fatigue–fracture tests under different isothermal conditions reveal that, the toughness values are higher in lower temperatures. The fractographical study of samples shows that, although some of the molding compound particles are left on the LF surface, the interfacial fracture is the dominant failure mode.