Lifetime and manufacturability of integrated power electronics

Abstract

In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially.Power electronics is a prerequisite to enable the exponential growth of power density.Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42K/W by the construction of a double side chip cooling.A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe.This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000VDC. The outlook onto an integrated 120A 700V SiC MOSFET demonstrator is given.