The warpage and stress simulation study of embedded organic substrate

Abstract

In recently years, the continued demand for electronic systems and subsystems with more functionality, higher electrical performance, smaller size and lower cost, the conventional packaging and interconnect technologies already can not be met for it's requirement, so system-in-package (SiP) modules have been growing rapidly. As a packaging technology platform, SiP allows a high degree of flexibility, high-density, high-speed, high performance, and multi-function in the package architecture. But, the form factor and electrical performance of system-in-package(SiP) is still continue to be driven by the next generation portable electronics. Recently, many company and research institute addressed embedded active and passive substrate technology development is the one of approach for the requirement. However, there are many electrical and mechanical reliability issues in embedded substrate. A mismatch of coefficient of thermal expansion (CTE) among substrate materials and structure can lead to large warpage, stress, delamination, crack or copper via break in the substrate. Thermal deformations and thermal stresses may occur due to mismatches of the coefficient of thermal expansion, Tg (Temperature of Glass transition), Young's modulus among the substrate materials during assembly process as well as service conditions, which lead to serious quality problems and failure of the products. It were conducted to be analyzed the stress and warpage during thermal cycle loading by Finite Element Method (FEM). At the beginning, a FE model was created; FE calculations were carried out in order to study the different substrate core and prepreg material effect on warpage and stress during thermo-mechanical history. And then, different substrate thickness, embedded component quantity also be conducted to analyze the warpage and stress during thermal history. For interface stress between via and prepreg material of embedded capacitor or die substrate, the CTE of core material which is closed to Cu via CTE (16.3 ppm/°C) generates lower via shear stress. For capacitor component stress, the CTE of core material which is closed to passive (12.3ppm/°C) & via land (16.3ppm/°C) generates lower component shear stress. For die stress, the CTE of core material which is closed to die (2.6ppm/°C) generates lower component shear stress.