Conventional VLSI Research Articles

Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs

At the 3 nm node, a hybrid-row-height design paradigm has emerged for better power efficiency and performance optimization. A diverse cell library that includes multiple variants of a cell with different fin counts is available. Instead of using cells with the same fin count for the entire chip, a design may combine cells with two different fin counts. Cells with the same fin count can be laid down in the same row resulting in a chip with hybrid row heights. With this brand-new design paradigm, revisiting and revamping the conventional VLSI placement flow becomes necessary. There were attempts that addressed the placement problem associated with hybrid-row-height design at the global placement stage or the placement legalization stage. In this work, we first propose an effective detailed placement approach suitable for hybrid-row-height designs and then conduct a comprehensive study to evaluate the different options of forming a complete hybrid-row-height design placement flow. For the first time, the advantage of considering the row configuration early on in the global placement stage is confirmed. Besides, our proposed detailed placement approach can improve the final half-perimeter wirelength by over 7% on average which more than double the improvement obtainable by a basic detailed placement algorithm similar to the well-known FastDP.

Hardware Trojan Detection Using Machine Learning: A Tutorial

With the growth and globalization of IC design and development, there is an increase in the number of Designers and Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no option but to use external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan (HT) . An HT can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fail to detect HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a Trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful in helping eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this tutorial, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN) -assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.

(Invited, Digital Presentation) Silicon Compatible Quantum Computers: Challenges in Devices, Integration, and Circuits

Quantum computers have been attractive because they could realize large-scale and highly complicated calculations that conventional computers cannot solve within a finite time. The large-scale integration of qubits, which are the building block of quantum computers, is required to realize their practical application. Indeed, fault-tolerant quantum computers require the integration of one million qubits. Therefore, silicon qubits is a high-profile candidate because they have advanced process and miniaturization technologies developed with VLSI. In addition, silicon qubits are advantageous in operation temperature. Superconductor qubits operate at the cryogenic temperature at around a few tens mK; in contrast, the operation principle of silicon qubits can operate at a much higher temperature over 1 K. The high-temperature operation can realize quantum computers with small and high-power refrigerators; therefore, we can expect desktop quantum computers instead of ongoing supercomputer-size ones. We must promote integration technology development for silicon qubits; however, the silicon qubit research was mainly in the physics field. Then, nowadays, the integration technology development is accelerated in the world.The challenges are in all conventional research fields: devices, integration, and circuits. We must re-develop the silicon technologies for quantum. For example, on the device design, now we do not have a good tool to design the qubits like TCAD; therefore, we must re-develop the TCAD technologies for quantum [1]. Actually, this is the starting point of our recent research activities; we are going to develop a quantum device simulator, clarify the requirements on the fabrication process of silicon qubits, and propose new technologies to reduce the variability to realize large-scale integration [2]. As for the integration, the quantum calculation circuits require several integrated items: qubits, qubit couplers, micro-magnets, and readout systems. The situation is quite different from the conventional VLSI case for which only the transistors should be integrated. Therefore, we must go re-developing new technologies to integrate all these items. Regarding the circuits, we must use CMOS circuits to generate input signals for qubits and readout the results of quantum calculation, which should be operated at cryogenic temperature. This is so-called “cryo-CMOS.” We must explore a new side of the transistor technologies, which is not investigated so far, because the physics of the MOSFET operation is quite different from the conventional room-temperature operation, hampering the circuit design due to the lack of the device operation model. In this situation, despite the long history of MOSFETs, new phenomena of transistor operation are discovered. For example, the low-frequency current noise increases at a low temperature. The origin of the noise is on the interface traps, instead of the fixed charges in the gate oxides as is the case for room temperature operation [3]. Therefore, we must re-developing CMOS circuit technologies from the bottom of the technologies, device physics.In this presentation, I’m going to overview the status of silicon technology developments for quantum from the viewpoints of devices, integration, and circuits. Also, we introduce some of our recent results to contribute to the developments.Acknowledgment: Our work is supported by MEXT Quantum Leap Flagship Program (Q-LEAP) JPMXS0118069228.[1] H. Asai et al., IEEE Electron Devices Technology and Manufacturing Conference 2021.[2] S. Iizuka et al., Tech. Dig. Symp. VLSI Technology 2021.[3] H. Oka et al., Tech. Dig. Symp. VLSI Technology 2020.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

Implementation of Fast Radix-10 BCD Multiplier in FPGA

Background: Multiplication is the basic operation in any signal processing systems and financial applications, all these applications requires multiplication to be performed in a faster and efficient manner on a silicon chip. Methods: This paper describes the algorithm and architecture of a BCD parallel multiplier. The design exploits two properties of redundant BCD codes to speed up its computation. Namely, the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition to this, number of new techniques are used in order to reduce significantly latency, area and for implementation on FPGA compared to existing implementations. Findings: Parallel architecture is used for generating partial products using radix-10 recoding technique for signed-digit of a BCD multiplier having set of digits between the range [–5, 5] and a positive set of multiplicand multiples coded in XS-3. Use of this encoding has various advantages like, as XS-3 is a self-complementing code, finding a negative of it is by just complementing the bits of respective number. Also the redundancy in XS-3 code is utilized for generating multiplicand multiples in a simple, faster and a carry-free way. Implemented design has three stages. Partial product generation, reduction and final conversion to BCD. For to implement the design in hardware the partial product reduction architecture is modified here to use a bank of ripple carry adder trees. ODDS representation uses 4-bit binary encoding technique which is similar to non-redundant BCD code, for this reason conventional VLSI circuit techniques such as carry-save adders and compression trees can be used effectively to perform operations on decimal numbers. Conclusion: To show the advantages of the resulted design, RTL model for 8 × 8-digit and 16 × 16-digits multiplication has been synthesized and implemented in Virtex-5 FPGA device. Results shows that the multiplier is about 10–15% delay efficient with existing work and about 14–18% area efficient.

(Invited) Synthesis, Properties and Applications of Group IV Graphane Analogues

In this talk, we will summarize our recent work on the synthesis, properties, and applications of a new family of two-dimensional materials based on sp3-hybridized Group IV elements. Ligand-terminated Si, Ge, and Sn graphane analogues are an emerging and unique class of two-dimensional materials that offer the potential to tailor the structure, stability, and properties via covalent chemistry. The presence of a fourth bond on the surface of the layers allows these materials to have the surface terminating ligand to be exchanged with a variety of organic functional groups. These materials feature a direct band gap which can be tuned with the surface ligand and the main group element. These materials can be synthesized as robust single crystals in gram-scale quantities, exfoliated into single layers, and prepared on conventional VLSI substrates as few-layer thin films. Furthermore, these graphane analogues are resilient towards oxidation and thermal degradation. Additionally, we will describe our recent studies on the electronic and thermal properties of these systems. Overall, this class of two-dimensional materials are not only promising building blocks for a variety of conventional semiconductor applications, but also provides a pioneering platform to systematically and rationally control material properties using covalent chemistry.

A new approach of presenting reversible logic gate in nanoscale.

Conventional lithography-based VLSI design technology deployed to optimize low-powered-computing and higher scale integration of semiconductor components. However, this downscaling trend confronts serious challenges of tunneling and leakage current increment to the Complementary Metal–Oxide–Semiconductor (CMOS) technology on nanoscale regimes. To resolve the physical restriction of the CMOS, Quantum-dot Cellular Automata (QCA) technology dedicates for the nanoscale technology that embrace a new information transformation technique. However, QCA is limited to the design of the sequential and combinational circuits only. This paper presents some highly scalable features reversible logic gate for the QCA technology. In addition, proposed layout compared with CMOS technology, offer a better reduction in size up to 233 times.

Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking; in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.

Fast Radix-10 Multiplication Using Redundant BCD Codes

We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speedup its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition, new techniques are developed to reduce significantly the latency and area of previous representative high-performance implementations. Partial products are generated in parallel using a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-5, 5], and a set of positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) coded in XS-3. This encoding has several advantages. First, it is a self-complementing code, so that a negative multiplicand multiple can be obtained by just inverting the bits of the corresponding positive one. Also, the available redundancy allows a fast and simple generation of multiplicand multiples in a carry-free way. Finally, the partial products can be recoded to the ODDS representation by just adding a constant factor into the partial product reduction tree. Since the ODDS uses a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, such as binary carry-save adders and compressor trees, can be adapted efficiently to perform decimal operations. To show the advantages of our architecture, we have synthesized a RTL model for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$16\times 16$</tex-math></inline-formula> -digit and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$34\times 34$</tex-math></inline-formula> -digit multiplications and performed a comparative survey of the previous most representative designs. We show that the proposed decimal multiplier has an area improvement roughly in the range 20-35 percent for similar target delays with respect to the fastest implementation.

Digital Implementation of Artificial Neural Network for Function Approximation and Pressure Control Applications

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data

The emergence of the nanometer scale integration technology made it possible for systems-on-a-chip, SoC, design to contain many reusable cores from multiple resources. This resulted in higher complexity SoC testing than the conventional VLSI. To address this increase in design complexity in terms of data-volume and test-time, several compression methods have been developed, employed and proposed in the literature. In this paper, we present a new efficient test vector compression scheme based on block entropy in conjunction with our improved row-column reduction routine to reduce test data significantly. Our results show that the proposed method produces much higher compression ratio than all previously published methods. On average, our scheme scores nearly 13% higher than the best reported results. In addition, our scheme outperformed all results for each of the tested circuits. The proposed scheme is very fast and has considerable low complexity.

A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

In this paper, we propose a high-performance droplet router for a digital microfluidic biochip (DMFB) design. Due to recent advancements in the biomicro electromechanical system and its various applications to clinical, environmental, and military operations, the design complexity and the scale of a DMFB are expected to explode in the near future, thus requiring strong support from CAD as in conventional VLSI design. Among the multiple design stages of a DMFB, droplet routing, which schedules the movement of each droplet in a time-multiplexed manner, is one of the most critical design challenges due to high complexity as well as large impacts on performance. Our algorithm first routes a droplet with higher by passibility which is less likely to block the movement of the others. When multiple droplets form a deadlock, our algorithm resolves it by backing off some droplets for concession. The final compaction step further enhances timing as well as fault tolerance by tuning each droplet movement greedily. The experimental results on hard benchmarks show that our algorithm achieves over 35 x and 20 x better routability with comparable timing and fault tolerance than the popular prioritized A* search and the state-of-the-art network-flow-based algorithm, respectively.

A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small—only about 3498μm2 based on TSMC 0.18μm standard cell technology.

Application-independent defect tolerance of reconfigurable nanoarchitectures

Self-assembled nanofabrication processes yield regular and reconfigurable devices. However, defect densities in this emerging nanotechnology are higher than those in conventional lithography-based VLSI. In this article, we present an application-independent defect tolerant design flow to minimize customized postfabrication design efforts to be performed per chip. In this flow, higher level design steps are not needed to be aware of the existence and the location of defects in the chip. Only a final mapping step is required to be defect aware. Application independence of this flow minimizes the number of per-chip design steps, making it appropriate for high volume production. We also present two mapping algorithms, recursive and greedy, which make the connection between defect-unaware design steps and the final defect-aware mapping step. Experiments show that the results obtained by the greedy algorithm are very close to the exact solutions. Using these algorithms, we analyze the manufacturing yield of molecular crossbars under different defect distribution models. We report on the size of the minimum crossbar to be fabricated such that a defect-free crossbar of the desirable size can be found with a guaranteed manufacturing yield.

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.

Development of a multitechnology field-programmable gate array suitable for photonic information processing

The architecture of a novel, multitechnology field-programmable gate array (FPGA) is introduced. Based on conventional complementary metal-oxide semiconductor VLSI technology this architecture has demonstrated the feasibility of reconfigurable and programmable hardware for prototyping photonic information processing systems. We report that this new FPGA architecture will enable the design of reconfigurable systems that incorporated technologies outside the traditional electronic domain. The smart photoreceivers monolithically integrated in the new FPGA architecture can receive optically encoded signals in parallel and process them with user programmable logic hardware.

The Enhanced Dielectric and Insulating Properties of Al2O3Modified Ta2O5Thin Films

Future-generation memory devices will require materials with higher dielectric constants compared to conventional dielectric materials such as silicon oxide and silicon nitride. Tantalum oxide (Ta2O5) is one of the most promising high dielectric constant materials because of its ease of integration into conventional VLSI processes compared to other complex oxide dielectrics. The dielectric constant and thermal stability characteristics of bulk Ta2O5 samples were previously reported to enhance significantly through small substitutions of Al2O3. However, this improvement in the dielectric constant of (1 − x)Ta2O5-xAl2O3 was not clearly understood. The present research attempts to explain the higher dielectric constant of (1 − x)Ta2O5-xAl2O3 by fabricating thin films with enhanced dielectric properties. A higher dielectric constant of 42.8 was obtained for 0.9Ta2O5-0.1Al2O3 thin films compared to that reported for pure Ta2O5 (25–30). This increase was shown to be closely related to a-axis orientation. Pure Ta2O5 thin films with similar a-axis orientation also exhibited a high dielectric constant of 51.7, thus confirming the orientation effect. Systematic study of dielectric and insulating properties of (1 − x)Ta2O5-xAl2O3 thin films indicate improved leakage current properties and reliability characteristics such as temperature coefficient of capacitance and bias stability with increase in Al2O3 concentrations.

Piezoelectric biomems

Objective: These days, smart MEMS are extensively used in the newly developed systems. Generally, the MEMS are developed by using conventional VLSI technology. These material used can be semiconductor, polymer, or biological. Mostly, Silicon type MEMs structures are used for making different types of micro-sensors or nano-devices. In this paper, the emphasis is placed on the development of piezoelectric types MEMs for various scientific and biomedical applications. A comparative study, for the combination of materials like Silicon and biological and Silicon and polymer is also mentioned.

Fine pattern fabrication on glass surface by imprint lithography

Fabrication of fine grating on a glass surface is achieved by imprint lithography using a Si 3N 4/SiO 2/Si mold and a low T g glass. A fine Si based mold is fabricated by a conventional VLSI process and the mold is directly pressed to a thin glass plate using a hot-press machine. The imprint conditions are designed based on the measured visco-elastic properties of the glass. Sub-micron patterns down to 250 nm in line width are successfully fabricated on the glass surface at low temperature without fatal errors. As the line width becomes smaller, higher pressures are required to achieve full compression. The surface of the imprinted glass is very flat.

Silicon LEDs fabricated in standard VLSI technology as components for all silicon monolithic integrated optoelectronic systems

It is shown that, by using conventional VLSI design rules and device processing, a variety of two terminal and multiterminal integrated silicon light-emitting devices (Si-LEDs) can be routinely fabricated without any adaptation to the process, enabling the production of all-silicon monolithic optoelectronic systems. Their specific performance can be tailored by their different geometries and structures, yielding, by design, area, line, and point light-emitting patterns. The light-generating mechanisms are based on carrier quantum transitions in Si pn junctions, operated in the field emission or avalanche modes. Field emission Si-LEDs can operate at supply voltages compatible with those of integrated circuits (5 V or less). Avalanche Si-LEDs require higher operating voltages, but yield higher light intensities. The two terminal Si-LEDs yield a linear relation between the emitted light intensity and the driving current. The multiterminal Si-LEDs exhibit a nonlinear relation between the light emission intensity and the controlling electrical signal, enabling signal processing operations, which can not be attained in two terminal Si-LEDs. Two basic structures of multi terminal Si-LEDs are presented, i.e MOS-like structures, or carrier injection based structures (BJT-like devices). They possess different input impedances and both their emitted light intensities and emitting area patterns can be controlled by the input electrical signal.