Conventional VLSI Research Articles

To Booth or not to Booth

Booth Recoding is a commonly used technique to recode one of the operands in binary multiplication. In this way the implementation of a multipliers’ adder tree can be improved in both cost and delay. The improvement due to Booth Recoding is said to be due to improvements in the layout of the adder tree especially regarding the lengths of wire connections and thus cannot be analyzed with a simple gate model. Although conventional VLSI models consider wires in layouts, they usually neglect wires when modeling the delay. To make the layout improvements due to Booth recoding tractable in a technology-independent way, we introduce a VLSI model that also considers wire delays and constant factors. Based on this model we consider the layouts of binary multipliers in a parametric analysis providing answers to the question whether to use Booth Recoding or not. We formalize and prove the folklore theorems that Booth recoding improves the cost and cycle time of ‘standard’ multipliers by certain constant factors. We also analyze the number of full adders in certain 4 2 -trees.

Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology

The room temperature-operation of a single-electron metal-oxide-semiconductor (MOS) memory with a defined quantum dot fabricated by sidewall patterning technique based on conventional VLSI technologies has been demonstrated without the aid of electron beam (EB) lithography for the first time. Sidewall patterning technique shows a good uniformity and controllability as well as high throughput. The fabricated memory devices show quantized threshold voltage shifts at room temperature. Time-dependant measurement of drain current shows discrete electron injection to the quantum dot. In addition, fabricated devices have good subthreshold swing and retention characteristics.

Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

A self-aligned epitaxially grown channel MOSFET device architecture for strained Si/SiGe systems

We describe the fabrication of a self-aligned epitaxially grown channel MOSFET device suitable for the strained Si/SiGe systems. This device architecture relies on a selective epitaxy process to achieve self-alignment and contact formation of the source and drain. It is also amenable in a conventional Si VLSI manufacturing environment. Difficulties encountered with growing high quality source/drain contacts to the channel layer were highlighted and a novel solution was proposed. Structural as well as electrical characterisation of the completed devices are presented.

Microsystems for multi-sensory data-acquisition

Data acquisition systems containing transducers, analog readout circuits and digital data processing capability having dimensions comparable to conventional silicon VLSI are feasible in silicon. The on-chip integration of these functions has been demonstrated and is a sound concept for the fabrication of an integrated silicon smart sensor for a single parameter. However, the complexity and data processing required in a data acquisition system for several quantities makes the concept, although technologically feasible, not economically viable. Partitioning of the various system functions over several dies and applying wafer-to-wafer bonding or using the multi-chip module is a more economically viable approach. Enhanced functionality can be obtained by using an active silicon platform as the substrate that contains all the infrastructural functions common to any instrument, such as power/thermal management, self-test and self-calibration and a local bus. In integrated chemical analysis systems, the additional advantage would be the slightly reduced packaging problem.

Moisture sensitive field effect transistors using gate structure

A humidity sensing device, named a moisture sensitive field effect transistor (HUMIFET) has been fabricated on an n-type Si wafer using conventional VLSI technology. A series of sensors, each having area have been designed on a single Si wafer. The FET device is an n-channel MISFET with a duplex gate structure. A humidity sensitive layer of an anodically oxidized film of Al covers the under-gate electrode area and serves as a humidity sensitive film. The structure of the HUMIFET is and a thin porous gold (Au) layer on acts as the upper gate electrode. The device shows an enhancement mode characteristics with a threshold voltage of V at 33% relative humidity (RH) level which increases with decreasing RH level. The capacitance of the sensing film is measured and its temperature dependence is also observed. The drain current of the device is measured with RH at constant gate and drain voltages and the hysteresis area is found. The sensitivity of the device is 4.8 for the whole range of RH levels at constant gate and drain voltages. During a one month study on reproducibility, the device is found to be very stable. The response and recovery times of the device are and s respectively.

VLSI ‘HyperNeuron’ for recognition of analog patterns

A new artificial neural circuit that performs recognition of multi-dimensional analog patterns is introduced. The circuit, named a ‘HyperNeuron’ is implemented using conventional CMOS VLSI technology and operates in subthreshold mode to perform high-speed recognition of input patterns at very low current levels. The HyperNeuron was designed to produce a sigmoidal output in order to support conventional neural network applications and techniques. The design has several advantages including: recognition of fully analog patterns, tuneable behavior, asynchronous operation, low current drain, and the ability to generalize patterns.

2D DWT VLSI architecture for wavelet image processing

A cost-effective VLSI architecture with separate data-paths and their corresponding filter structure is proposed for performing a two-dimensional discrete wavelet transform (2D DWT). Compared with the conventional 2D DWT VLSI architectures, the proposed semi-recursive 2D DWT VLSI architecture has minimum hardware cost, and optimised data-bus utilisation, scheduling control overhead and storage size.

Si nanofabrication using AFM field enhanced oxidation and anisotropic wet chemical etching

We present a novel Si nanofabrication method based on an atomic force microscope (AFM) field-enhanced oxidation and an anisotropic wet chemical etching using SIMOX (separation by implanted oxygen) wafer. A newly developed AFM system enables this fabrication method to be fully compatible with a conventional VLSI process. Using this technique, Si quantum wire with a feature size of 60 nm has been successfully fabricated within the intended area. Moreover, by means of a structural analysis by cross-sectional transmission electron microscopy, it is confirmed that the AFM-field-enhanced oxide film has a similar excellent structure as thermally grown oxide.

Characterization and Application of Materials Grown by Electron-Beam-Induced Deposition

Electron-beam-induced deposition of materials has been known for almost 40 years from contamination writing. It has developed into “additive lithography” with nanometer resolution employed in scanning electron microscopes, in dedicated lithography systems, in reducing image projection systems, and in scanning tunneling microscopes. The technique allows deposition of nanometer- to micrometer-size structures with nanometer precision in three dimensions without supplementary process steps such as lift-off or etching procedures. Depending on the deposition conditions, novel compound materials are created from organometallic precursors which form resistors with a resistivity ranging from 103 Ω· cm to 2×10-3 Ω· cm and sustain current densities higher than 5×105 A/cm2 without damage. High-resolution transmission electron microscope analysis of the deposits reveals a new class of nanocrystalline compound materials. Crystals of metals or metalcarbides and oxides are immersed in a matrix of carbonaceous material. The deposition process is compatible with conventional VLSI technology. Tips for atomic force and scanning tunneling microscopy can be produced with radii of curvature as small as 5 nm. Field electron emission is obtained from deposited tips starting at an extraction voltage of 8 V and yielding 180 µ A of current at 20 V. Three-dimensional conducting structures can be produced as sensors.

Field programmable gate arrays. A cheaper way of customizing product prototypes

Advances in VLSI technology have brought very complex digital systems onto a very small area of silicon. However, the design cycle times associated with the conventional VLSI designs have called for a technology that will support very rapid system prototyping. Also, the non-recurring engineering (NRE) costs associated with existing VLSI technologies are very high. An ideal design style should support rapid prototyping at almost no or very nominal NRE costs. FPGA is an attempt in this direction. FPGAs have a potential for matching both speed and density of mask programmed gate arrays (MPGAs). It is expected that more and more digital designs will be built on FPGAs, and FPGA based designs will outnumber the MPGA based designs in the near future. The author begins by discussing the nature of FPGAs and their architecture (with design tools). The author goes on to discuss custom computing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A feedforward artificial neural network based on quantum effect vector-matrix multipliers

The vector-matrix multiplier is the engine of many artificial neural network implementations because it can simulate the way in which neurons collect weighted input signals from a dendritic arbor. A new technology for building analog weighting elements that is theoretically capable of densities and speeds far beyond anything that conventional VLSI in silicon could ever offer is presented. To illustrate the feasibility of such a technology, a small three-layer feedforward prototype network with five binary neurons and six tri-state synapses was built and used to perform all of the fundamental logic functions: XOR, AND, OR, and NOT.

Resonant tunneling quantum-dot diodes: physics, limitations, and technological prospects

The authors discuss the electronic structure and properties of the present generation of resonant-tunneling quantum-dot structures. Quantum dots are zero-dimensional semiconductor nanostructures, i.e., structures in which an electron is quantum-mechanically confined in all three spatial dimensions. Quantum dots appear to represent a viable structure to allow the continued downscaling of critical circuit geometries beyond the currently perceived limits for conventional VLSI devices. As they are currently fabricated, however, quantum-dot diodes have impediments which prevent the full realization of their potential. The authors assess these limitations and discuss measures for their solution. >

A pipelined associated memory implemented in VLSI

A memory system which rapidly chooses the stored item most closely matching a given input is fundamental to a number of recognition tasks. A memory architecture which performs this function is discussed. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates and is amenable to implementation using conventional digital VLSI fabrication process. These characteristics are demonstrated by a prototype device fabricated using the MOSIS 3- mu m CMOS design rules, which can compare more than two million 9-bit input works per second. Behavioral simulations demonstrate the applicability of the architecture to some basic recognition tasks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Yield estimation for serial superchip

A yield model is developed to estimate yield values for the serial superchip. The superchip is a large silicon chip containing many processing elements together with a communication network. Owing to its large area, the superchip concept will not be economically viable if current silicon processing technology and conventional non-redundant VLSI design techniques are employed to implement it. This paper demonstrates the result of yield improvement by employing hardware redundancy. Cost-effectiveness is also measured by the optimality of the employed redundancies.

On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the advantages of optical over electrical interconnects for conventional two-dimensional VLSI and wafer-scale-integrated circuits have not been clearly demonstrated, for dense multiwafer WSI or hybrid-WSI three-dimensional architectures, the ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages. While optical waveguides are readily fabricated in the wafer plane, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one method of meeting this criterion. Using optical devices operating at wavelengths beyond the Si absorption cutoff, low-loss through-wafer propagation between WSI circuit planes can be achieved over the distances of interest (≈ 1 mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that >90 percent transmittance can be obtained through p-type silicon. Initial results show a 400-percent source-detector coupling enhancement is obtainable for these optical interconnections using VLSI process-compatible SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> phase-reversal zone plate lenses.

An associative memory based on an electronic neural network architecture

A high-density matrix of α-Si resistors was made to demonstrate a new type of parallel-processing associative memory consisting of an interconnected array of analog amplifiers. The 22 × 22 resistor matrix was made using a technology compatible with conventional VLSI processing. This demonstration circuit can recall up to four 22- bit memories in 1 to 10 µs while correcting errors in the input word of at least 5 bits. This function is difficult to perform efficiently in conventional digital hardware and is the basis for solving a variety of pattern-recognition problems including vision and speech.

AT 2 = O(N log 4 N), T = O(log N) fast Fourier transform in a light connected 3-dimensional VLSI

We can perform a N-point FFT with time performance T=Ο(log N) and area-time performance AT 2 =Ο(N log 4 N), by using the 3-dimensional VLSI system which is optically interconnected. This performance exceeds the theoretical lower bound of the area-time performance (N 2 log 2 N) of the conventional VLSI.

Thermal instability of Schottky diode barrier heights modified by inert ion sputter-etching damage

The barrier height of Schottky diodes made to dry-etched silicon surfaces differs from those fabricated on wet chemically etched silicon. Some have suggested utilization of this phenomenon to yield diodes for VLSI applications that display barrier enhancement to p-type silicon and barrier reduction to n-type silicon together with good diode ideality factors; however, it is shown here that the modified barrier heights can be dramatically unstable even when exposed to relatively low-temperature cycling, thus rendering this technique of enhancing the barrier height to p-type silicon and reducing the barrier height to n-type silicon inappropriate for conventional VLSI fabrication. It is hypothesized that the barrier instability is due to a localized silicide reaction or surface reconstruction occurring at the metal/silicon interface.

Heterojunction Ohmic Contacts to Si Using Ge/Si n+/n+ Structures

ABSTRACTOhmic contacts to n-type Si have been formed using a thin n layer of Ge grown by selective-area molecular beam epitaxy. The n+Ge is used to lower the metal-semiconductor barrier energy and thus reduce the contact resistivity of the thin film structure. Al/n+Ge/n+Si test devices were fabricated in a manner compatible with conventional VLSI processing and consisted of a 3500 A thick layer of arsenic-doped Ge grown at 250°C on a selectively diffused, phosphorus-doped Si substrate. Using both four terminal Kelvin and transmission line devices, unsintered Al/Ge/Si structures exhibited contact resistivities a factor of five lower than Al/Si control devices, in agreement with theoretical calculations based on a simple tunneling model for the metal/Ge/Si heterojunction ohmic contact.