Conventional Solid-phase Crystallization Research Articles

Underlayer Selection to Improve the Performance of Polycrystalline Ge Thin Film Transistors

1. Introduction To improve the performance of Ge-thin film transistors (TFTs), it is essential not only to enhance the crystallinity of poly-Ge but also comprehensively study the relationship between its electrical properties and TFT characteristics. We recently advanced conventional solid-phase crystallization (SPC) method, significantly enlarged the grain size of poly-Ge and recorded the highest Hall effect hole mobility (μ Hall) of 620 cm2/Vs [1,2]. We fabricate poly-Ge TFTs using SPC-Ge and discuss the relationship between the film properties and TFT characteristics [3]. In the present study, we discuss the Ge thickness effects on the poly-Ge TFTs. To further improve the TFT performance, we enhanced the Ge crystallinity at thin film region (< 100 nm) by inserting Al2O3 underlayer. 2. Experimental Procedure The a-Ge layers were deposited on SiO2 glass substrates by vacuum deposition while heating at 125 °C. The initial film thickness of the a-Ge layer (t i) ranged from 25 to 200 nm. The samples were also prepared in which the insulating underlayer (Al2O3, GeO2) was sputtered at 10-50 nm for Ge with t i = 50-300 nm. The samples were then loaded into a conventional tube furnace in an N2 atmosphere annealed at 450 °C for 5 h to induce SPC.We fabricated accumulation-mode metal source/drain (S/D) p-channel TFTs using SPC-Ge. Figure 1 shows the process and structure. Pt and TiN were sequentially formed as a metal S/D and a capping layer, respectively. We used Al/SiO2/Al2O3/SiO2/GeO2 for the gate stack. The channel width and length (W/L) were 55 and 10 μm, respectively. All process including SPC were conducted below 450 °C. 3. Results and Discussion Figures 2(a)‒2(e) show the grain size dramatically varies with t i. All samples showed p-type conduction because the defects in Ge provides shallow acceptor levels that generate holes at room temperature. Therefore, larger grain sizes provide lower hole concentration p, as shown in Figs. 2(f) and 2(g). Figure 2(g) also shows that μ Hall peaks at t i = 200 nm, whereas the grain size peaks at t i = 100 nm. This behavior is likely attributed to the carrier scattering near the Ge/SiO2 interface [2].Figure 2(h) shows that on-current I on increases with increasing t i, which reflects μ Hall. Off-current I off is determined by the relationship between t i and the maximum depletion layer width (d max), which can be estimated from p. From the relationship between d max and t i, we found that the lower t i provides the higher occupation of the depletion layer in the whole SPC-Ge layer, which decreases I off. Reflecting I on, I off, and the on/off current ratio I on/I off reaches the maximum at t i = 50 nm. Figure 2(i) shows that field-effect mobility (μ FE) is consistent with the trend of μ Hall, while μ FE is much lower than μ Hall. This is likely because not only carrier scattering at the MOS interface, but also large I off causes underestimation of transconductance and μ FE.We thinned the t i = 100 nm sample to 55 nm using chemical-mechanical polishing. The film keeps low p enough to get full-depleted, and was processed into TFT as before. Figures 3(a) and 3(b) show the typical p-channel transistor operation, high I on/I off (102) and μ FE (170 cm2/Vs) because of both the high I on due to the high μ Hall and low I off. Therefore, to improve the TFT performance, a Ge layer compatible with high μ Hall and a thin film is desirable.Because the nucleation in a thin film occurs at the substrate interface, we modulated the interface by preparing Al2O3 and GeO2 underlayers. Figures 4(a)‒4(f) show the grain size is almost doubled by inserting underlayers for both t i = 50 nm and 300 nm, while the t i = 50 nm Ge layer with GeO2 did not crystallize completely due to the slow growth rate. Compared to the samples without underalyers, Fig. 4(g) shows the underlayers reduce p reflecting the large grain size. Figures 4(h) shows the GeO2 underlayer provides high μ Hall for t i = 300 nm, while low μ Hall for t i < 300 nm. This behavior is likely due to the carrier scattering near the Ge/GeO2 interface. Conversely, the Al2O3 underlayer provides high μ Hall for t i < 300 nm. In particular, the t i = 50 nm Ge layer exhibits relatively low p and high μ Hall. These results suggest that the Al2O3 underlayer has the potential to further improve the performance of poly-Ge TFTs.

Silver-induced layer exchange for polycrystalline germanium on a flexible plastic substrate

Crystalline Ge was directly achieved on a flexible plastic by layer exchange between Ag and amorphous Ge layers. The key factor for the layer exchange was limiting the diffusion of Ag to Ge by lowering the growth temperature (250 °C) and controlling the condition of an interlayer (1-nm-thick SiO2) between Ag and Ge. The layer exchange using Ag provided much faster nucleation and lateral growth rates of Ge compared with the conventional solid-phase crystallization and Al-induced layer exchange. A principle to determine the materials for layer exchange is proposed from the perspective of the diffusion and solubility of metals and semiconductors.

Low temperature synthesis of highly oriented p-type Si1-xGex (x: 0–1) on an insulator by Al-induced layer exchange

A composition tunable Si1-xGex alloy has a wide range of applications, including in electronic and photonic devices. We investigate the Al-induced layer exchange (ALILE) growth of amorphous Si1-xGex on an insulator. The ALILE allowed Si1-xGex to be large grained (&amp;gt; 50 μm) and highly (111)-oriented (&amp;gt; 95%) over the whole composition range by controlling the growth temperature (≤ 400 °C). From a comparison with conventional solid-phase crystallization, we determined that such characteristics of the ALILE arose from the low activation energy of nucleation and the high frequency factor of lateral growth. The Si1-xGex layers were highly p-type doped, whereas the process temperatures were low, thanks to the electrically activated Al atoms with the amount of solid solubility limit. The electrical conductivities approached those of bulk single crystals within one order of magnitude. The resulting Si1-xGex layer on an insulator is useful not only for advanced SiGe-based devices but also for virtual substrates, allowing other materials to be integrated on three-dimensional integrated circuits, glass, and even a plastic substrate.

The nc-Si films with controlled crystal structure and electrical conductivity via the re-crystallization approach

Nanocrystalline silicon (nc-Si) films were synthesized via different re-crystallization approaches from amorphous silicon (α-Si:H) films deposited using plasma enhanced chemical vapor deposition (PECVD). The microstructure evolution with various annealing conditions was investigated via high resolution transmission electron microscopy (HRTEM) and Raman spectrometry. It was found that, compared with the conventional solid phase crystallization (SPC) annealing, a rapid thermal process (RTP) pre-annealing at 600°C for 60s can significantly enhance the recrystallization process and the electrical conductivity of nc-Si films. In addition, for the nc-Si films with similar crystal sizes, it was uncovered that the logarithm of conductivity presented a linear relationship with the crystalline volume fraction. This study has therefore been an important step forward to the future synthesis of the nc-Si films with manipulated microstructure and electrical conductivity for further applications.

New Crystallization Method of Amorphous Silicon by Selective Area Heating for Stamp Process

We propose a new crystallization technique called selective area heating. In this study, we investigated a new technique for high-reliability selective area crystallization of a-Si films that does not cause thermal damage to glass substrates. We reduced the crystallization time as compared to the conventional solid phase crystallization method using a stamp-type isolated thin heater. The thin heater was fabricated with a layer of Pt on a quartz substrate via Ta adhesion and capping layers. A crystalline transverse optic phonon peak at about 519 cm−1 was seen in Raman scattering spectra, showing that the films were crystallized. The poly-Si grain size was found to be smaller than 100 nm, and the dendritic structure was found using scanning electron microscopy.

Effects of gate insulator using high pressure annealing on the characteristics of solid phase crystallized polycrystalline silicon thin-film transistors

The oxidizing ambient was built using high pressure H2O vapor at 550 °C. For the solid phase crystallization (SPC) polycrystalline silicon (poly-Si) that is annealed for 1 h at 2 MPa, the oxide thickness is about 150 Å. The oxide layer is approximately 90 Å above the original surface of the poly-Si and 60 Å below the original surface. The oxide layer is used as the first gate insulator layer of thin-film transistors (TFTs). The heating at 550 °C with 2 MPa H2O vapor increased the carrier mobility from 17.6 cm2/V s of the conventional SPC process to 30.4 cm2/V s, and it reduced the absolute value of the threshold voltage (Vth) from 4.13 to 3.62 V. The subthreshold swing also decreased from 0.72 to 0.60 V/decade. This improvement is attributed mainly to the reduction in defect density at the oxide/poly-Si interface and in the poly-Si film by the high pressure annealing (HPA) process. Since the realization of excellent performance at the oxide/poly-Si interface and in poly-Si depends on the defect density, the poly-Si having the thermal oxide formed by a combined process of SPC and HPA may be well suited for fabrication of poly-Si TFTs for flat panel displays such as active matrix organic light emitting diodes.

Low-temperature solid-phase crystallization of amorphous SiGe films on glass by imprint technique

Low-temperature (<500°C) solid-phase crystallization (SPC) of amorphous Si1−xGex (x: 0–0.7) films was examined on insulating substrates by using Ni-imprint technique. Incubation time for SPC was remarkably reduced by catalytic effects without changing growth velocity. As a result, Ni-free large SiGe grains (∼4μm) were obtained at controlled positions. The crystallinity of the grown regions was almost the same as that of poly-SiGe formed by the conventional high temperature SPC at 600°C.

High-Performance Solid-Phase Crystallized Polycrystalline Silicon Thin-Film Transistors with Floating-Channel Structure

High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with a floating-channel active region (FC poly-Si TFTs) are proposed in this study. A high-quality poly-Si channel film accompanied by a larger grain size and fewer microstructural defects could be obtained. Compared with the conventional poly-Si TFTs (CN poly-Si TFTs), the fabricated FC poly-Si TFTs exhibit superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, and lower trap state density. These electrical performance improvements could be attributed to the fact that the α-Si film with a floating-channel structure can relieve the stress generated from the crystallization process accompanying the trap state density reduction and grain size enhancement. In addition, the FC poly-Si TFTs also exhibit improved hot-carrier stress immunity due to the reduced weak Si–H bonds from fewer grain boundaries in the poly-Si channel. Therefore, the proposed FC poly-Si TFTs can be easily fabricated by conventional solid-phase crystallization, and suitable for future high-performance flat-panel display applications.

Effects of high pressure annealing on the characteristics of solid phase crystallization poly-Si thin-film transistors

Integrating circuits into organic light emitting diode displays require fabrication of polycrystalline silicon (poly-Si) based thin-film transistors (TFTs) on glass substrates. In this work we evaluated the use of high pressure annealing (HPA) process of poly-Si films in H2O atmosphere to improve TFT characteristics via reducing defect density in poly-Si films. We attempted to develop a HPA process at temperatures below 600°C without causing any glass distortion and reducing the throughput. The HPA-treated poly-Si film was analyzed using various spectroscopic methods such as Raman, x-ray photoelectron spectroscopy, and transmission electron microscope, and the evaluation of the characteristics of TFTs fabricated by such poly-Si films was made. The heating at 550°C with 1MPa H2O vapor increased the carrier mobility from 8.5to20cm2∕Vs and reduced the absolute value of the threshold voltage from 9.6to6.5V, as compared with the conventional solid phase crystallization (SPC) process. The sub-threshold swings also decreased from 1.2to0.8V/decade. Since the realization of good performance in poly-Si depends on the defect density, the poly-Si formed by a combined process of SPC and HPA may be well suited for fabrication of poly-Si TFTs for flat panel displays such as liquid crystal display and active matrix organic light emitting diode that require circuit integration on panels.

Ni-imprint induced solid-phase crystallization in Si1−xGex (x: 0–1) on insulator

Position control of solid-phase crystallization in the amorphous Si1−xGex (x: 0–1) films on insulating substrates was investigated by using Ni-imprint technique. Crystal nucleation at the imprinted positions proceeded approximately 2–20 times, depending on Ge fraction, faster than the conventional solid-phase crystallization, which was due to the catalytic effect of Ni. As a result, large SiGe crystal regions (∼2μm) were obtained at controlled positions. On the other hand, the growth velocity did not changed, which suggested that grown regions contained few residual Ni atoms.

Experimental and molecular dynamics study on crystallization of amorphous silicon under external fields

Solid-phase crystallization (SPC) of amorphous silicon (a-Si) under an external force field is investigated experimentally and numerically. Experimental results show that the kinetics of crystallization can be greatly enhanced by applying induction fields without the heating problems of a-Si film and its substrate, since temperature rises during the crystallization process are negligibly small. To explore the underlying acceleration mechanisms for the SPC process under the external fields, molecular dynamics simulations are carried out using the Tersoff potential. The numerical amorphous structure is obtained by the liquid quenching method and is utilized to simulate the crystallization processes at various process temperatures with and without external force fields. While homogeneous crystallization of a-Si could not be achieved readily, it is shown that the heterogeneous crystallization can be significantly accelerated by external force fields. This enhancement is due to increased molecular jumping frequencies associated with the molecular potential energies being increased by external excitations, rather than due to thermal mechanisms dominant in conventional SPC processes.

Heterogeneous crystallization of amorphous silicon expedited by external force fields: a molecular dynamics study

Applying a molecular dynamics simulation technique with the Tersoff potential, we investigate the isothermal crystallization processes of amorphous silicon (a-Si). To obtain a realistic amorphous structure, a rapid quenching process from liquid-phase at 3500 K to solid-phase at 500 K is simulated at a rate of 1012 K/s and the Voronoi analysis is conducted to observe atomic structural changes during this cooling process. This amorphous structure is utilized to simulate the crystallization processes at various process temperatures with and without external force fields. While homogeneous crystallization of a-Si could not be achieved readily, it is shown that the heterogeneous crystallization can be significantly accelerated by external force fields. This enhancement is owing to increased molecular jumping frequencies associated with the molecular potential energies being increased by external excitations, rather than due to thermal mechanisms normally found in conventional solid-phase crystallization processes.

Heterogeneous crystallization of amorphous silicon expedited by external force fields: a molecular dynamics study

Applying a molecular dynamics simulation technique with the Tersoff potential, we investigate the isothermal crystallization processes of amorphous silicon (a-Si). To obtain a realistic amorphous structure, a rapid quenching process from liquid-phase at 3500 K to solid-phase at 500 K is simulated at a rate of 10 12 K/s and the Voronoi analysis is conducted to observe atomic structural changes during this cooling process. This amorphous structure is utilized to simulate the crystallization processes at various process temperatures with and without external force fields. While homogeneous crystallization of a-Si could not be achieved readily, it is shown that the heterogeneous crystallization can be significantly accelerated by external force fields. This enhancement is owing to increased molecular jumping frequencies associated with the molecular potential energies being increased by external excitations, rather than due to thermal mechanisms normally found in conventional solid-phase crystallization processes.

Metal induced crystallization of SiGe at 370°C for monolithically integrated MEMS applications

Over the last decade SiGe has been proposed as a structural material for low thermal budget microelectromechanical systems (MEMS) that can be post-processed on top of standard CMOS driving and controlling electronics [1-6]. There are several ways to decrease the deposition temperature of SiGe and at the same time preserve the desired physical properties for MEMS as low electrical resistivity, high quality factor, economical growth rate and low mean stress and strain gradient. The conventional approach to reduce the crystallization thermal budget is to increase the germanium content to 60%, or more, using conventional Low Pressure Chemical Vapor Deposition (LPCVD) [1-3]. In this case highly conductive polycrystalline films can be realized, but the strain gradient is relatively high. This can be eliminated by furnace annealing at 450°C [2], which might introduce damage to the underlying circuits such as in the case of Cu/low k CMOS. This problem can be alleviated using excimer pulsed laser annealing [7, 8], which has been attractive for low thermal budget applications such as thin film transistors (TFT) [9], solar cells fabricated on glass substrates [10] and for monolithic integration of MEMS devices on top of standard driving electronics using SiGe as an active material [8, 11]. Also the use of hydrogenated microcrystalline SiGe allows for a low thermal budget [12]. In addition, metal induced crystallization has recently been proposed to enhance the crystallization of silicon at temperatures as low as 500°C, and the realized devices had outstanding performance compared to those employing conventional solid-phase crystallization [13]. This technique enhances crystallization by two methods. First, it has been observed that depositing SiGe on top of a thin Al or Ni layer, has a polycrystalline micro-structure close to the metal/ SiGe interface [11]. Annealing this film for a long period (is determined by the annealing temperature), results in metal diffusion and a subsequent crystallization of the film. Finally, when the metal is diffused completely through out the film, it can be etched away. The main disadvantage of this approach is that the mean stress is highly compressive and this might affect the functionality of surface micromachined structures [13].

Low-Temperature-Processed Polycrystalline silicon thin-film transistors Using a New Two-Step Crystallization Technique

Low-temperature-processed (LTP) Polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated with a poly-Si film crystallized by a new two-step crystallization (NTSC) technique were investigated. The NTSC is characterized by the combination of excimer-laser-induced formation of nucleation centers and short-time low- temperature furnace annealing to create clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSC poly-Si film not only exhibit better performance but also significantly shorten the crystallization time (about 6 h at 600°C) as compared to those fabricated using conventional solid phase crystallization (about 20 h or longer at 600°C).

A Novel Two-Step Annealing Technique for the Fabrication of High Performance Low Temperature Poly-Si TFTs

Low temperature processed (LTP) poly-Si thin film transistors (TFTs) fabricated with a poly-Si film crystallized by a novel two-step annealing (NTSA) technique were investigated and compared with those using conventional solid phase crystallization (SPC) and excimer laser annealing (ELA) schemes. The NTSA scheme is characterized by the combination of an excimer laser induced formation of nucleation centers and a short-time low temperature furnace annealing (about 6 h at 600°C) creating clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSA poly-Si film not only exhibit a better performance but also significantly shorten the crystallization time as compared to those fabricated using the conventional SPC (about 20 h or longer at 600°C). In addition, the uniformity of the device characteristics for the devices using the NTSA scheme is superior to that using the ELA scheme and is comparable to that using the SPC scheme. © 2003 The Electrochemical Society. All rights reserved.

CMOS Application of Single-Grain Thin Film Transistor Produced Using Metal Imprint Technology

A novel technology which is termed metal imprint has been developed for positioning and growing large thin-film Si grains on amorphous substrates. The metal imprint is carried out using Ni coated Si tip arrays and crystallization is carried out in solid phase. This technology enables us to fabricate a grain-boundary-free thin-film transistor (TFT) in a single-grain by aligning the position of the channel and that of the imprinted site. Single-grain TFTs having the channel in the single-grains which were fabricated using a high temperature process showed the field effect mobility up to 450 cm2/Vs for n-channel and up to 260 cm2/Vs for p-channel. Single-grain TFTs showed better threshold controllability than TFTs fabricated on Si films prepared by conventional solid phase crystallization (SPC). Complementary-metal-oxide-semiconductor (CMOS) circuits composed of single-grain TFTs have been fabricated. CMOS inverters composed of single-grain TFTs showed superior transfer characteristics to that composed of SPC-polycrystalline Si TFTs. The 3-µm CMOS ring oscillator which operated with the supply voltage down to 2 V showed the propagation delay time of less than 6.7 ns/stage at 7 V.

Comparison Study of Metal Induced Lateral Crystallized and Solid-Phase Crystallized Polycrystalline Silicon Thin Film Transistors with Different Channel Thickness

N- and P-type polycrystalline silicon thin film transistors are fabricated with channel thickness of 30 nm and 100 nm by metal induced lateral crystallization (MILC) and conventional solid-phase crystallization (SPC) of amorphous silicon. Significant improvement is obtained for the MILC devices by ultrathin channel layer. But for SPC devices, improvement is not as significant. The possible reasons are proposed and discussed.

Fabrication of high-mobility p-channel poly-Si thin film transistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (/spl les/500/spl deg/C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500/spl deg/C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of /spl sim/10/sup 7/ without post-hydrogenation. The mobility was measured to be as high as 90 cm/sup 2//V/spl middot/s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600/spl deg/C.

Device Characteristics of a Poly-Silicon Thin Film Transistor Fabricated by Milc at Low Temperature

AbstractHigh performance poly-Si thin film transistors were fabricated by using a new crystallization method, Metal-Induced Lateral Crystallization (MILC). The process temperature was kept below 500°C throughout the fabrication. After the gate definition, thin nickel films were deposited on top of the TFT's without an additional mask, and with a one-step annealing at 500°C, the activation of the dopants in source/drain/gate a-Si films was achieved simultaneously with the crystallization of the a-Si films in the channel area. Even without a post-hydrogenation passivation, mobilities of the MILC TFT's were measured to be as high as 120cm2/Vs and 90cm2/Vs for n-channel and p-channel, respectively. These values are much higher than those of the poly-Si TFT's fabricated by conventional solid-phase crystallization at around 6001C.