Conventional Metal-oxide-semiconductor Field-effect Transistor Research Articles

Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes

We have fabricated single-wall carbon nanotube field-effect transistors (CNFETs) in a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) structure, with gate electrodes above the conduction channel separated from the channel by a thin dielectric. These top gate devices exhibit excellent electrical characteristics, including steep subthreshold slope and high transconductance, at gate voltages close to 1 V—a significant improvement relative to previously reported CNFETs which used the substrate as a gate and a thicker gate dielectric. Our measured device performance also compares very well to state-of-the-art silicon devices. These results are observed for both p- and n-type devices, and they suggest that CNFETs may be competitive with Si MOSFETs for future nanoelectronic applications.

Physical Random-Number Generator Using Schottky MOSFET

A new physical random-number generator using a metal oxide semiconductor field-effect transistor (MOSFET) whose source and drain are made of Schottky contacts is proposed. MOSFETs, which have PtSi source and drain contacts, are fabricated on a silicon-on-insulator. It was found that large noise appears in the drain current of the PtSi Schottky-source/drain MOSFET when it is operated as an n-channel transistor. The noise spectrum in the frequency range up to 400 kHz shows that the noise is frequency-dependent, which is similar to the noise of a conventional pn-junction MOSFET. A circuit in which an inverter consisting of two Schottky MOSFETs is used as the noise source is proposed to create a random binary signal. The circuit is demonstrated to be able to create a binary signal array whose characteristic is close to a quasi-random number generated by a computer.

Study on bis[phthalocyaninato] praseodymium complex/silicon hybrid chemical field-effect transistor gas sensor

A new kind of sandwich-like bis[2,3,9,10,16,17,23,24-octakis(octyloxy)phthalocyaninato] Praseodymium complex Pr(Pc *) 2 [Pc *=Pc(OC 8H 17) 8] is used as film-forming material. Pure Pr(Pc *) 2 ultrathin film and Pr(Pc *) 2 and octadecanol(OA) mixed ultrathin films were prepared by the Langmuir–Blodgett (LB) technique. Based on the conventional metal-oxide–semiconductor–field-effect transistor (MOSFET), a new chemical field-effect transistor (ChemFET) gas-sensing device was fabricated by depositing the Pr(Pc *) 2/OA (1:3 molar ratio) mixed LB film on the gate area of MOSFET replacing the gate metal. The sensitive property of Pr(Pc *) 2/OA mixed LB film based ChemFET sensor to nitrogen dioxide (NO 2) gas is studied by the change of drain current ( I ds) during gas exposure. The Pr(Pc *) 2/OA mixed LB film ChemFET gas sensor can detect NO 2 gas down to 5 ppm. The qualities are attributed to amplification by the FET and the ordered nature of LB film. The mechanism of sensitivity of Pr(Pc *) 2/OA mixed LB film ChemFET to NO 2 is also studied in the paper.

Fabrication and characterization of metal-oxide-semiconductor field-effect transistors and gated diodes using Ta/sub 2/O/sub 5/ gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta/sub 2/O/sub 5/, gate oxide were fabricated. The Ta/sub 2/O/sub 5/ films were deposited by plasma enhanced chemical vapor deposition. The I/sub DS/-V/sub DS/ and I/sub DS/-V/sub GS/ characteristics mere measured. The electron mobility was 333 cm/sup 2//V/spl middot/s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5/spl times/10/sup 12/ cm/sup -2/ eV/sup -1/, 780 cm/s and 3/spl times/10/sup -6/ sec, respectively. A comparison with conventional MOSFETs using SiO/sub 2/ gate oxide was made.

A monolithically integrated Si interband tunneling diode (IBTD)/MOSFET memory for ultra low voltage operation below 0.5 V

A static random access memory (SRAM) cell circuit, constructed using Si interband tunneling diodes (IBTDs) and a metal-oxide-semiconductor field effect transistor (MOSFET), is presented. The Si-IBTD is a negative differential resistance (NDR) device with a tunneling dielectric between a degenerate p+-diffusion layer and an n+-poly-Si electrode. The Si-IBTD was monolithically integrated with the MOSFET on a silicon-on-insulator (SOI) wafer by a novel fabrication process and a compact SRAM cell circuit consisting of two Si-IBTDs and a MOSFET was fabricated. The Si-IBTD shows a full process compatibility with a conventional MOSFET process. Data-read/write operations of this SRAM cell circuit were successfully demonstrated at ultra-low voltage, below 0.5 V, even at room temperature. Simulation results showed that downscaling of the Si-IBTD size was effective for improving the circuit speed. A writing time of the memory cell with a Si-IBTD size of 0.1 μ m2was reduced to 0.8 ns in simulation. The Si-IBTD/MOSFET merged SRAM can be considered one of the most promising candidates for future low-power device applications.

Parasitic Resistance Reduction in Deep Submicron Dual-Gate Transistors with Partially Elevated Source/Drain Extension Regions Fabricated by Complementary Metal-Oxide-Semiconductor Technologies

Deep submicron dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with partially elevated source/drain (S/D) structures were fabricated using complementary MOS (CMOS) technologies. In comparison with well-defined conventional MOSFETs, it is revealed that the drivability is appreciably enhanced by the S/D elevation and, further, that a p-channel MOSFET gains more from the S/D elevation than an n-channel MOSFET. Investigation of the parasitic resistance is consistent with the results of the transistor characteristics.

Analysis of Short-Channel Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistor on Silicon-on-Insulator Substrate and Demonstration of Sub-50-nm n-type Devices with Metal Gate

The Schottky source/drain metal-oxide-semiconductor field-effect transistor (MOSFET) has potential for scaling to the nanometer regime, because low electrode resistances with very shallow extension can be realized using metal source/drain. In this study, very short channel n- and p-type Schottky source/drain MOSFETs with silicon-on-insulator (SOI) structure were analyzed theoretically, and n-type devices were demonstrated experimentally. It was shown theoretically that a drivability of the Schottky source/drain MOSFET comparable to that of conventional MOSFETs can be realized with a low Schottky barrier height. The short-channel effect can be suppressed even with a 15-nm-long channel at tOX = 1 nm and tSOI = 3 nm. The room-temperature operation of sub-50-nm n-type ErSi2 Schottky source/drain MOSFETs on a separation by implanted oxygen (SIMOX) substrate was demonstrated.

Full-band Monte Carlo investigation of hot carrier trends in the scaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-/spl mu/m). In addition, our results suggest that below 0.15 /spl mu/m, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated.

Two-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nm

We present simulation results of a silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET), which has a structure similar to that of a conventional MOSFET, but the source and drain regions are now entirely replaced by metals. By using abrupt metal/silicon Schottky junctions, short-channel effects are avoided. Based on a few commonly used physical assumptions, we have calculated the transistor characteristics, and we find that this new three-terminal transistor can offer gain and impedance isolation, desirable for logic circuit applications.

Single-Electron Transistor in Silicon-on-Insulator with Schottky-Contact Tunnel Barriers

We have proposed a novel single-electron transistor (SET) with Schottky tunnel barriers. The proposed SET can be fabricated by employing the standard salicide process and can be merged in the current CMOS VLSI (complementary metal-oxide-semiconductor-very-large-scale integration). We analyzed its characteristics using the Poisson equation and the master equation based on the semi-classical theory. Calculation results show that the proposed SET has good cutoff characteristics similar to those of conventional MOSFETs (metal-oxide-semiconductor-field-effect transistors) while its gate-periodic characteristics are similar to those of conventional SETs.

Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field-effect transistors

The phonon-limited mobility of strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two-dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two-dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain-induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valleys, contributes to the mobility enhancement in bulk strained Si, it is not necessarily adequate to explain the mobility enhancement for two-dimensional electrons in strained Si. This is suggested by the fact that the mobility limited by intravalley acoustic phonon scattering, which is the dominant scattering mechanism, has almost the same value in the two- and the fourfold valleys, because the difference in the conductivity mass is compensated by differences in the inversion-layer thickness and the valley degeneracy.

Reliability of Source-to-Drain Non-Uniformly Doped Channel (NUDC) MOSFETs for Sub-Quarter-Micron Region

We present an analysis of hot carrier degradation in source-to-drain nonuniformely doped channel (NUDC) metal oxide semiconductor field effect transistors (MOSFETs). Simulation has been performed in order to investigate the influence of the NUDC structure on the device characteristics. It is demonstrated that the hot carrier resistance of NUDC MOSFETs is almost the same as that of conventional MOSFETs when thin gate oxide is used. This is due to the drain electric field strength of NUDC MOSFETs, which becomes the same as that of conventional MOSFETs when the gate oxide is thin, since the drain electric field is not only affected by the channel impurity profile but also strongly influenced by the gate electrode.

Experimental investigation of a PtSi source and drain field emission transistor

A p-type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

Ballistic metal-oxide-semiconductor field effect transistor

Experiments on ultra-small metal-oxide-semiconductor field effect transistors (MOSFETs) less than 100 nm have been widely reported recently. The frequency of carrier scattering events in these ultra-small devices is diminished, so that further suppression of carrier scattering may bring these devices close to the regime of ballistic transport. Carrier scattering is suppressed by constructing their channel regions with intrinsic Si and also by low temperature operation. This article proposes the ballistic transport of carriers in MOSFETs, and presents the current-voltage characteristics of the ballistic n-channel MOSFET. The current is expressed with the elementary parameters without depending on the carrier mobility. It is independent of the channel length and is proportional to the channel width. The current value saturates as the drain voltage is increased and the triode and the pentode operation are specified as in the conventional MOSFET. Similar current-voltage characteristics in the ballistic transport regime are also investigated for the p-channel MOSFET, the dual gate ultra-thin silicon on insulator MOSFET, and the high electron mobility transistor device. The obtained current gives the maximum current limitation of each field effect transistor geometry. The current control mechanism of ballistic MOSFETs is discussed. The current value is governed by the product of the carrier density near the source edge in the channel, and the velocity with which carriers are injected from the source into the channel. Influence of optical phonon emission to the transport is discussed. It is suggested that if the device is operated with relatively low carrier density at low temperatures, and if the scattering processes other than the optical phonon emission are suppressed so as to attain the ballistic transport, the optical phonon emission is also suppressed and ballistic transport is sustained. A convenient figure of merit to show the ballisticity of carrier transport in an experimental MOSFET is proposed. Its value is estimated for some examples of the recent ultra-small MOSFET experiment. The proposed current voltage characteristics are evaluated for a dual gate silicon on insulator MOSFET geometry. The result is compared with the recently reported elaborate Monte Carlo simulation with satisfactory agreement.

Experimental investigation of silicon-on-insulator metal-oxide- semiconductor field-effect transistors at high magnetic field and low temperature

Shubnikov–de-Haas (SDH) oscillations as well as low-temperature measurements have been systematically performed in order to characterize thin-film silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). The two-dimensional properties of the SOI MOS inversion layers highly depend on the quality of the front and buried Si-SiO2 interfaces. The influence of interface coupling on the quantized SDH oscillations is assessed. Even in 70 nm thin films, the carriers remain essentially confined to the lowest subband at an interface. Parasitic effects such as series resistance influence have been carefully examined in the case of short-channel devices. It is also shown that for submicronic devices, the attenuation of the oscillations as a function of the lateral electric field strongly increases with channel length. Eventually, it is demonstrated that unlike conventional bulk silicon MOSFETs, a fully depleted SOI MOSFET allows studying charge localization in MOS inversion layers, without needing any temperature variation to estimate the density of localized electrons.