Conventional Metal-oxide-semiconductor Field-effect Transistor Research Articles

An ultralow voltage circuit for energy harvesting with 3.3 mW capacity

This brief describes an astable multivibrator aimed to low voltage energy harvesting using inductive coupling and bipolar junction transistors. The topology needs a bias voltage at the bases, and we propose a circuit called starting block to generate this voltage from the supply. A proof-of-concept circuit with discrete devices was able to work with a voltage as low as 50 mV and deliver 3.3 mW from a 100 mV supply. To the authors’ knowledge, it is the energy harvesting circuit with highest power capacity. It has the additional advantage of using conventional devices, in contrast with other approaches that use special devices like junction field effect transistors and native metal–oxide-semiconductor field effect transistors (MOSFETs). The circuit also needs a smaller transformer when compared to its version using conventional MOSFETs.

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

4H-SiC Double-Trench MOSFET with Side Wall Heterojunction Diode for Enhanced Reverse Recovery Performance

In this study, a novel 4H-SiC double-trench metal-oxide semiconductor field-effect transistor (MOSFET) with a side wall heterojunction diode is proposed and investigated by conducting numerical technology computer-aided design simulations. The junction between P+ polysilicon and the N-drift layer forming a heterojunction diode on the side wall of the source trench region suppresses the operation of the PiN body diode during the reverse conduction state. Therefore, the injected minority carriers are completely suppressed, reducing the reverse recovery current by 73%, compared to the PiN body diodes. The switching characteristics of the proposed MOSFET using the heterojunction diode as a freewheeling diode was compared to the power module with a conventional MOSFET and an external diode as a freewheeling diode. It is shown that the switching performance of the proposed structure exhibits equivalent characteristics compared to the power module, enabling the elimination of an external freewheeling diode in the power system.

Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications

This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron velocity, threshold voltage (V th), electron mobility, and sub-threshold swing (SS) of these devices has been performed. Results reveal a 43.85% improvement in SS and 9.83% decrement in V th for GaN-BTG-MOSFET. Furthermore, the frequency analysis has been performed in terms of scattering (S) parameters, cut-off frequency (f T) and maximum oscillator frequency (f MAX) to show how the device is also suitable for radio frequency applications. Furthermore, the study of parametric variation of GaN-BTG-MOSFET with the change in channel length, oxide thickness (t ox), and doping concentration has also been presented. Results show that GaN-BTG-MOSFET can act as a promising structure for further scaling down of the trenched MOSFET and assures better performance for sub-20 nm trenched MOSFET.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

Highly Efficient Switching Operation of 1.2 kV-Class SiC SWITCH-MOS

A 1.2 kV silicon carbide (SiC) SBD-wall-integrated trench metal oxide semiconductor field effect transistor (MOSFET) (SWITCH-MOS) exhibits potential for solving body-PiN-diode-related problems such as bipolar forward degradation and switching losses among relatively low breakdown voltage 1.2 kV-class SiC MOSFETs. In this study, dynamic characteristics and switching losses of the SWITCH-MOS and conventional MOSFET are compared. The results demonstrate that the SWITCH-MOS exhibits smaller turn-on and reverse recovery losses than a conventional MOSFET at high temperatures. Ruggedness performances such as short circuit and unclamped inductive switching capabilities were evaluated.

A Graphene/Polycrystalline Silicon Photodiode and Its Integration in a Photodiode-Oxide-Semiconductor Field Effect Transistor.

In recent years, the characteristics of the graphene/crystalline silicon junction have been frequently discussed in the literature, but study of the graphene/polycrystalline silicon junction and its potential applications is hardly found. The present work reports the observation of the electrical and optoelectronic characteristics of a graphene/polycrystalline silicon junction and explores one possible usage of the junction. The current–voltage curve of the junction was measured to show the typical exponential behavior that can be seen in a forward biased diode, and the photovoltage of the junction showed a logarithmic dependence on light intensity. A new phototransistor named the “photodiode–oxide–semiconductor field effect transistor (PDOSFET)” was further proposed and verified in this work. In the PDOSFET, a graphene/polycrystalline silicon photodiode was directly merged on top of the gate oxide of a conventional metal–oxide–semiconductor field effect transistor (MOSFET). The magnitude of the channel current of this phototransistor showed a logarithmic dependence on the illumination level. It is shown in this work that the PDOSFET facilitates a better pixel design in a complementary metal–oxide–semiconductor (CMOS) image sensor, especially beneficial for high dynamic range (HDR) image detection.

New Power MOSFET with Beyond-1D-Limit RSP-BV Trade-Off and Superior Reverse Recovery Characteristics.

The application of conventional power metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the famous one-dimensional “silicon limit” (1D-limit) in the trade-off relationship between specific on-resistance (RSP) and breakdown voltage (BV). In this paper, a new power MOSFET architecture is proposed to achieve a beyond-1D-limit RSP-BV trade-off. Numerical TCAD (technology computer-aided design) simulations were carried out to comparatively study the proposed MOSFET, the conventional power MOSFET, and the superjunction MOSFET. All the devices were designed with the same breakdown voltage of ~550 V. The proposed MOSFET features a deep trench between neighboring p-bodies and multiple p-islands located at the sidewall and bottom of the trench. The proposed MOSFET allows a high doping concentration in the drift region, which significantly reduces its RSP compared to the conventional power MOSFET. The multiple p-islands split the electric field into multiple peaks and help the proposed MOSFET maintain a similar breakdown voltage to the conventional power MOSFET with the same drift region thickness. Another famous device technology, the superjunction MOSFET (SJ-MOSFET), also breaks the 1D-limit. However, the SJ-MOSFET suffers a snappy reverse recovery performance, which is a notorious drawback of SJ-MOSFET and limits the range of its application. On the contrary, the proposed MOSFET presents a superior reverse recovery performance and can be used in various power switching applications where hard commutation is required.

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Thanks to their superior transport properties, indium gallium arsenide (InGaAs) metal–oxide–semiconductor field-effect transistors (MOSFETs) constitute an alternative to conventional silicon MOSFETs for digital applications at ultrascaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we: 1) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs dual-gate ultrathin body (DG-UTB) FETs and 2) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against multi-subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultrathin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This, in turn, implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.

Six Transistor Carbon Nanotube Field Effect Transistors Based RAM Design and Hardware Description Language Code Development

The goal of this thesis is to develop carbon nanotube field effect transistors (CNFETs) based static random-access memory (SRAM) and implement it into a Very-highspeed integrated circuit Hardware Description Language Analog and Mixed-Signal (VHDLAMS). To achieve this objective, a compact model of the transistor known as enhancementmode MOSFET-like SWCNT-CNFET is used. This circuit-compatible model of CNFET is described using VHDL-AMS and tested for basic electrical characteristics. This model is valid for CNFETs with channel lengths greater than 20 nm. Based on the CNFETs a new SRAM is designed, and implemented in VHDL-AMS. The performance of the proposed SRAM cell is investigated and compared with SRAMs from conventional metal-oxide semiconductor field effect transistors (MOSFETs). The effect of substrate biasing a CNFET is also demonstrated and implemented in designing the SRAM cell. The VHDL-AMS codes of the CNFET and the SRAM are simulated in software known as Ansoft Simplorer. The compact model of the CNFET is organized hierarchically in three main levels. The first level models the intrinsic channel just beneath the gate of the transistor. The second level builds upon the first level and models the doped source and drain regions of the CNFET. The last level represents the complete trans-capacitance model of the transistor and accounts for multiple CNTs. The proposed SRAM cell is composed of four CNFETs and two load resistors. The driver CNFETs of the proposed SRAM cell are substrate biased. Besides, 8-bit complete SRAM architecture based on this cell is indicated. The performance analysis of the SRAM shows that it has better writing and reading speed as well as better stability when compared with SRAM from conventional MOSFETs. Specifically, the newly proposed SRAM cell has read time of twenty five pico seconds, write time of twenty pico seconds and can tolerate a noise of 120 mV at 32 nm node technology.

A Nano junctionless Double-Gate MOSFET by Using the Charge Plasma Concept to Improve Short-Channel Effects and Frequency Characteristics

In this study, a junctionless double-gate metal-oxide semiconductor field-effect transistor (MOSFET) is investigated by using the concept of charge plasma. The n+ charge plasma in source and drain regions is created electrically in the double-gate MOSFET (CPSD-MOSFET) using additional appropriate metals without applying doping. The results showed that the structure is like a conventional MOSFET, which can improve some electrical parameters. It protects the proposed structure from some limitations such as random doping oscillations and short-channel effects bearing its conventional structure. In addition, high temperature and annealing processes are unnecessary for making the source/drain doping of the CPSD-MOSFET because their regions are created electrically. Thus, the thermal budget step is removed. Furthermore, the proposed structure has some improvements as compared to the junctionless transistor structure, and it can overcome the main problem of this structure, namely the high off current. In general, in the proposed structure, the charge plasma idea changes the charges and depletion regions besides the channel and improves the short-channel effects such as hot electron effect and leakage current because of the improved electric field.

High Stable and Low Power 8T CNTFET SRAM Cell

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Sub-30nm In2O5Sn gate electrode recessed channel MOSFET: A biosensor for early stage diagnostics

This paper presents a technology computer-aided design (TCAD) analysis of an ultrasensitive In2O5Sn gate (transparent gate) recessed channel (TGRC) metal-oxide-semiconductor field effect transistor (MOSFET) as a biosensor for early-stage disease diagnostics. The key parameters such as sensitivity, switching ratio, and threshold voltage shift have been compared with the conventional MOSFET. For immobilizing the protein molecules, a cavity has been embedded in the gate insulator region due to which gate capacitance changes owing to the accumulation of protein molecules which reflects the deviation in threshold voltage. Higher sensitivity (1.542) is achieved for protein at a very low drain bias (0.2 V) in comparison to streptavidin and APTES ((3-Aminopropyl) triethoxysilane). Moreover, the cavity gap variation (from 8 to 15 nm) and oxide thickness limitation has also been observed for the device as a biosensor. All the results pave way for early detection techniques of protein-related diseases such as Alzheimer's diseases, ovarian cancer and coronary artery disease with the existing complementary metal oxide semiconductor (CMOS) technology.

Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs

This manuscript describes an experimental comparative study of effects of the total ionizing dose (TID) on the main electrical parameters and figures of merit of Metal–Oxide–Semiconductor Field Effect Transistors (MOSFETs) implemented with two different layout styles, i.e., the hexagonal gate shape (diamond MOSFET, DM) and its corresponding rectangular counterparts (Conventional MOSFET, CM), which they were irradiated with a low dose rate with gamma-rays (60Co-source), considering that both present the same gate areas (AG), channel widths (W), aspect ratios (W/L), and concerning two different bias conditions (OFF and ON states) during the irradiation procedure. The main results of this work show that, besides the diamond MOSFETs present a better electrical performance than those found in their Conventional MOSFETs counterparts, they are also capable of boosting their ionizing radiation tolerances (smaller variation of the threshold voltage, subthreshold slope and minimize IDS leakage, etc.). Furthermore, it was observed that the hexagonal gate shape with a α angle equal to 90° tends to be the best gate geometry for MOSFETs because it is capable of enhancing the TID tolerance, intrinsically, in relation to the CM counterparts, regarding gamma-rays source used in this study. Therefore, the diamond layout style with α angle of 90° can be considered an alternative Hardness-By-Design layout technique which is able to manufacture planar MOSFETs low-cost, high electrical performance, and high ionizing tolerance to be applied in the space, medical, and nuclear CMOS ICs applications.

(Invited) SiC Lateral MOSFETs Implemented on Semi-Insulating Substrate

4H-SiC lateral metal-oxide-semiconductor field effect transistor (MOSFET) were fabricated on on-axis high purity semi-insulating (HPSI) SiC substrate without using epitaxial layer. The lateral MOSFET adopted current path layer (CPL) between gate and drain region for obtain MOSFET characteristics. The CPL was formed by ion-implantation and acts like a drift region of the conventional lateral MOSFET. By using semi-insulating substrate and CPL, 1093 V of breakdown voltage (BV) and 89.8 mΩ·cm2 of specific on-resistance (Ron,sp) were obtained with 20 μm long CPL. Experimentally extracted field-effect channel mobility was 21.7 cm2/V·s and the figure-of-merit (FoM, BV2/Ron,sp) was 13.3 MW/cm2.

Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET

This paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson’s equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model.

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with $${N}^{+}{-}{P}^{-}$$ N + - P - junction

We propose herein a new dual-gate metal---oxide---semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an $${N}^{+}$$N+ region on the source side with the rest consisting of a $${P}^{-}$$P- region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an $${N}^{+}$$N+ region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, $${I}_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.

(Invited) Investigation of Critical Interfaces in Few-Layer MoS2 Field Effect Transistors with High-k Dielectrics

Transition metal dichalcogenides (TMDs) as 2D or few-layer semiconducting channel material are being widely studied to lower power consumption and obtain negligible short channel effects with continued transistor scaling [1-4]. Meanwhile, research needs to be conducted on top-gated, metal-oxide-semiconductor field effect transistors (MOSFETs) to correctly assess the possibility of TMDs supplanting silicon in the channel region. This is because top-gate device architectures face some key integration challenges that typical bottom-gate TMD FET structures do not experience. As an example, molybdenum disulfide (MoS2) is supposed to have no dangling interfacial bonds, making it difficult to form high-k dielectrics on them. Therefore, surface functionalization of TMDs has attracted attention [5-12]. However, detailed understanding on performance of transistors with metal/high-k/TMD top-gate stacks are still lacking. In addition, a major hurdle of incorporating these two-dimensional (2D) materials in device structures of any kind is the high contact resistance at the metal/TMD interface [13-15]. Recent results have shown that the backside dielectric can influence top-gate MOSFET performance [16]. In this work, few-layer MoS2 FET-based devices were fabricated using top and bottom high-k dielectrics (Al2O3 and/or HfO2). The C-V response of a top-gate, HfO2/MoS2 gate stack on a backside SiO2 layer demonstrated the existence of specific defects at the interface, which demonstrated frequency dependent “humps” in depletion – similar to conventional Si MOSFETs with unpassivated silicon dangling bonds in the dielectric/Si interfacial region. Also, a comparison of UHV and HV metal deposition on MoS2 as contacts for source and drain was done where results demonstrated that UHV deposited metals were superior to HV ones. In an additional experiment with Al2O3 as the bottom-gate dielectric layer, the intrinsic mobility and subthreshold slope were greatly improved compared to SiO2 or HfO2 as back gate dielectric FETs, indicating a positive influence on top-gate device performance even without any backside bias. Furthermore, a forming gas anneal is found to further enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation. Another significant finding in top-gate FET performance is the high-k dielectric screening effect of the backside Al2O3 layer. Results demonstrate that the extracted top-gate field effect mobility values are higher compared to SiO2 or HfO2 as a backside oxide – even though all FETs have the same top-side HfO2 dielectric oxide and no back bias. Acknowledgement – This work was supported in part by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, Science Foundation Ireland under the US-Ireland R&D Partnership Programme Grant Number SFI/13/US/I2862, and the center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA.

High performance multi-finger MOSFET on SOI for RF amplifiers

In this paper, we propose structural modifications in the conventional planar metal–oxide–semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.