Parasitic Resistance Reduction in Deep Submicron Dual-Gate Transistors with Partially Elevated Source/Drain Extension Regions Fabricated by Complementary Metal-Oxide-Semiconductor Technologies

Abstract

Deep submicron dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with partially elevated source/drain (S/D) structures were fabricated using complementary MOS (CMOS) technologies. In comparison with well-defined conventional MOSFETs, it is revealed that the drivability is appreciably enhanced by the S/D elevation and, further, that a p-channel MOSFET gains more from the S/D elevation than an n-channel MOSFET. Investigation of the parasitic resistance is consistent with the results of the transistor characteristics.