Conventional Gate Oxide Research Articles

EFFECTS OF SCALING OF JUNCTIONLESS TRANSISTOR PARAMETERS WITH SILICON DIOXIDE (SIO2) AND SILICON NITRATE (SI3N4) GATE OXIDES ON THE ELECTRICAL CHARACTERISTICS OF THE DEVICES

This research investigated the effects of scaling of parameters of junctionless transistors (JLT) with SiO2 gate oxide and Si3N4 gate oxide on the electrical characteristics of the two devices. It also compared the electrical performance of the two devices as a way of replacing the conventional SiO2 gate oxide with high-k dielectric such as Si3N4 gate oxide. Different JLT were designed and simulated using a technology computer aided device software, sentaurus and extracted the electrical characteristics such as Threshold voltage, subthreshold slope, drain induced barrier lowering, on-state current etc. It was observed that leakage current, DIBL, SS as well as on-state current were significantly improved using Si3N4 as gate oxide in JLT. As a result, on-state to off-state current ratio was greatly increased, hence the speed of the device. The performance was significantly increased to approximately 109 using Si3N4 material for gate length of 10nm and nanowire diameter of 10nm. All these were achieved because of the high dielectric constant, k of the Si3N4 which is higher than that of SiO2. Similarly, Si3N4 has also has high energy band gap which considerably help in reducing the leakage current and other short channel effects (SCEs).

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

The discovery of a third breakdown: phenomenon, characterization and applications

In the history of metal–oxide–semiconductor field effect transistor (MOSFET), the quality of its gate oxide has been a cornerstone of the present semiconductor integrated circuits. The changes of gate dielectrics from conventional SiO2 gate oxide into high-k materials has brought us more challenges in various aspects of transistors, especially the reliability improvement when MOSFET dimension is continually scaled. Depending on the making of high-quality gate dielectrics, it plays a major role for the manufacture of high-end CPU with ultra-low power and low leakage, nowadays. There are two major well-known breakdowns in MOSFET’s history. Not until 2015, a world first observation of the breakdown, different from soft and hard breakdown, named dielectric fuse breakdown, dFuse, was discovered, as a result of CMOS technology moving into the high-k metal-gate (HKMG) era. In this paper, we will introduce from the inception of the Ig-RTN (random telegraph noise) measurement on the understanding of breakdown in 2008 and briefly describe the fundamentals of the RTN technique. Later in 2015, a version 2.0 of this Ig-RTN measurement, named Ig-transient, was successfully developed to delineate the breakdown path in HKMG transistors, from which a third breakdown, named dielectric fuse breakdown, was discovered. Its origin and physical mechanism have been discussed. This breakdown relies on the understanding of a leakage path in the gate dielectric of MOSFET, especially the movement of oxygen ions and the oxygen vacancies in the gate dielectric. Sophisticated measurement technique has also been developed to identify the traps generated in the gate dielectrics which laid the foundations on the understanding of trap generation as a function of time. In the end, two major applications in memories are presented, one is in the use of one-time-programming memory and the other on the understanding of the switching phenomena involved in the operation of resistance random-access memory (RRAM).

High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29 % improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO2|La2O3|HfO2 (HLH) Sandwich Gate Dielectrics

In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) are investigated. To increase the ON-current and pixel intensity, and control the voltage stress bias, the conventional gate oxide material (silicon dioxide, SiO2) is replaced with a tri-high-k gate dielectric layer, hafnium dioxide (HfO2)/lanthanum oxide (La2O3)/hafnium dioxide (HfO2)—(HLH). Further, the performance of the proposed DG-DAL structure is compared with the single-active-layer (SAL) and dual-active-layer (DAL) TFTs. The amorphous indium-gallium zinc-oxide (a-IGZO) is considered as active layer for SAL channel region, and on the other hand, a-IGZO and indium-tin-oxide (ITO) are considered as active layers for DAL TFT and DG-DAL TFT channel regions. The parameters such as OFF-current, ON-current, ION/IOFF ratio, threshold voltage, mobility, average subthreshold swing, etc. are evaluated for the considered structures. It is observed that the DG-DAL TFT with HLH dielectric offers high ON-current of 3.85 × 10–3 A/μm, very low OFF-current of 2.53 × 10–17 A/μm, very high ION/IOFF ratio of 1.51 × 1014, threshold voltage of 0.642 V, high mobility of 35 cm2 v–1 s–1 and average subthreshold swing of 127.84 mV/dec. A commercial TCAD simulation tool ATLAS from SilvacoTM is used to investigate all the parameters for considered structures.

Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material

<p><span>In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance <br /> (LP) technology. </span></p>

Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO-=SUB=-2-=/SUB=-/La-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=-/HfO-=SUB=-2-=/SUB=- (HLH) Sandwich Gate Dielectrics

In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) is investigated. To increase the ON-current and pixel intensity, and control the voltage stress bias, the conventional gate oxide material (silicon dioxide SiO2) is replaced with a tri-high-k gate dielectric layer, hafnium dioxide HfO2/lanthanum oxide La2O3/hafnium dioxide HfO2 (HLH). Further, the performance of the proposed DG-DAL structure is compared with the single-active-layer (SAL) and dual-active-layer (DAL) TFTs. The amorphous indium-gallium zinc-oxide (a-IGZO) is considered as active layer for SAL channel region, and on the other hand, a-IGZO and indium-tin-oxide (ITO) are considered as active layers for DAL TFT and DG-DAL TFT channel regions. The parameters such as OFF-current, ON-current, ION/IOFF ratio, threshold voltage, mobility, average subthreshold swing, etc. are evaluated for the considered structures. It is observed that the DG-DAL TFT with HLH dielectric offers high ON-current of 3.85·10-3 A/μm, very low OFF-current of 2.53·10-17 A/μm, very high ION/IOFF ratio of 1.51·1014, the threshold voltage of 0.642 V, high mobility of 35 cm2·v-1·s-1 and average subthreshold swing of 127.84 mV/dec. A commercial TCAD simulation tool ATLAS from SilvacoTM is used to investigate all the parameters for considered structures. Keywords: single active layer (SAL), dual active layer (DAL), double-gate dual active layer (DG-DAL), InGaZnO (IGZO), InSnO (ITO), thin-film transistor (TFT), HfO2/La2O3/HfO2 (HLH).

U shaped vertical gate bulk MOSFET for area minimization

For the first time, design, and analysis of vertical gate MOSFET is presented in this paper. This structure consumes significant less area compared to conventional horizontal gate-oxide bulk MOSFET for 7 nm technology generation and onwards. This simple structure also wave offs all complicated fabrication steps needed for formation of gate spacer. The functionality of vertical gate MOSFET or VGMOSFET is found to lie within close proximity to the guidelines of 2013 edition of International Technology Roadmap for Semiconductors or ITRS. All simulation works are done by Sentaurus TCAD software.

Synthesis and Dielectric Studies of Monoclinic Nanosized Zirconia

Zirconium dioxide is a prospective high-κmaterial that can replace silicon dioxide. Zirconium dioxide nanoparticle has been synthesized using sol-gel process at room temperature. The structural and morphological characterization of the nanoscaled zirconium dioxide is done using FTIR, SEM, X-ray diffraction, and TEM. The particle size of the synthesized ZrO2is observed in the range of 50–80 nm with an average crystallite size of 2–10 nm. The results are compared with commercial coarse zirconia which showed a particle size in the range of 900 nm–2.13 µm and crystallite size of 5.3 nm–20 nm. It is expected that both nanoscaling and the high dielectric constant of ZrO2would be useful in replacing the low-κSiO2dielectric with high-κZrO2for CMOS fabrication technology. The synthesized ZrO2is subjected to impedance analysis and it exhibited a dielectric constant of 25 to find its application in short channel devices like multiple gate FinFETS and as a suitable alternative for the conventional gate oxide dielectric SiO2with dielectric value of 3.9, which cannot survive the challenge of an end of oxide thickness ≤ 1 nm.

Atomic Layer Deposition of SiN for spacer applications in high-end logic devices

Continuous down scaling of transistor size resulted in introduction of high-k material to replace the conventional gate oxide. High-k Metal Gate implementation brings new challenges to the subsequent processing steps of the device. Both oxide ingress and removal of the HKMG stack during later cleaning steps must strictly be avoided. We have developed and optimized an ALD SiN encapsulation liner which protects the HKMG stack and also serves as a robust spacer for subsequent ion implantation. SiN was chosen because of its oxide-blocking characteristics and its durability in diluted hydrofluoric acid. We developed sophisticated ALD processes using ionized ammonia radicals and dichloro-silane. This ALD process has several advantages compared to conventional LPCVD or PECVD processes: Superior thickness control and uniformity, excellent step coverage and no loading effects. In addition, process temperature could be reduced to 500°C, which is shown to be critical for protecting the HKMG stack. Further reduction in process temperature to 400°C is also demonstrated using a novel precursor.

True Reference Nanosensor Realized with Silicon Nanowires

Conventional gate oxide layers (e.g., SiO(2), Al(2)O(3), or HfO(2)) in silicon field-effect transistors (FETs) provide highly active surfaces, which can be exploited for electronic pH sensing. Recently, great progress has been achieved in pH sensing using compact integrateable nanowire FETs. However, it has turned out to be much harder to realize a true reference electrode, which--while sensing the electrostatic potential--does not respond to the proton concentration. In this work, we demonstrate a highly effective reference sensor, a so-called reference FET, whose proton sensitivity is suppressed by as much as 2 orders of magnitude. To do so, the Al(2)O(3) surface of a nanowire FET was passivated with a self-assembled monolayer of silanes with a long alkyl chain. We have found that a full passivation can be achieved only after an extended period of self-assembling lasting several days at 80 °C. We use this slow process to measure the number of active proton binding sites as a function of time by a quantitative comparison of the measured nonlinear pH-sensitivities to a theoretical model (site-binding model). Furthermore, we have found that a partially passivated surface can sense small changes in the number of active binding sites reaching a detection limit of δN(s) ≈ 170 μm(-2) Hz(-1/2) at 10 Hz and pH 3.

High-Speed Memory from Carbon Nanotube Field-Effect Transistors with High-κ Gate Dielectric

We demonstrate 100 ns write/erase speed of single-walled carbon nanotube field-effect transistor (SWCNT-FET) memory elements. With this high operation speed, SWCNT-FET memory elements can compete with state of the art commercial Flash memories in this figure of merit. The endurance of the memory elements is shown to exceed 104 cycles. The SWCNT-FETs have atomic layer deposited hafnium oxide as a gate dielectric, and the devices are passivated by another hafnium oxide layer in order to reduce surface chemistry effects. We discuss a model where the hafnium oxide has defect states situated above, but close in energy to, the band gap of the SWCNT. The fast and efficient charging and discharging of these defects is a likely explanation for the observed operation speed of 100 ns which greatly exceeds the SWCNT-FET memory speeds of 10 ms observed earlier for devices with conventional gate oxides.

Depth profiling of ultra-thin oxynitride gate dielectrics by using MCs 2+ technique

Ultra-thin silicon oxynitride (SiO x N y ) is the leading candidate to replace pure silicon oxide (SiO 2) before high k dielectrics come into place because oxynitrides demonstrate several properties superior to those of the conventional gate oxides. The performance of the transistor was reported to depend on the N dose and its distribution in the gate oxide. Therefore, accurate characterization of SiO x N y is prerequisite to control the quality of the ultra-thin nitrided gate oxide. However, secondary ion mass spectrometry (SIMS) faces big challenges in analyzing ultra-thin gate oxide because of surface effect and matrix effect. In this work, MCs 2 + (M stands for matrix element) was detected to reduce the matrix effect in depth profiling the ultra-thin oxynitride. However, N profile was very close to the top surface if the oxynitirde was fabricated by decoupled plasma nitridation (DPN). With the conventional approach, the N dose was overestimated and the N profile was distorted near the top surface. To obtain a reliable N profile, the oxynitride was capped with a thin layer of oxide. The N profile of interest was hence in the region of sputtering equilibrium, i.e. the surface effect was minimized. As the results, reliable N dose and profile have been obtained.

Ionising radiation and electrical stress on nanocrystal memory cell array

In this work, we have investigated the effects of irradiation and electrical stress of nanocrystal memory cell arrays. Heavy ion irradiation has no or negligible immediate effects on the nanocrystal MOSFET characteristics, and on the programming window of the cells. By electrically stressing irradiated device, we see accelerated oxide breakdown similar to that previously observed on conventional thin gate oxide MOS capacitors, but no appreciable change of the degradation kinetics in terms of programming window closure and shift. The accelerated breakdown is ascribed to the degradation of the oxide–nitride–oxide (ONO) layer used as control oxide after exposure to ionising irradiation.

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Evaluation of<tex>$hboxSiO_2$</tex>Antifuse in a 3D-OTP Memory

We have evaluated an antifuse technology used in a novel three-dimensional one-time-programmable (3D-OTP) nonvolatile solid-state memory. The 3D-OTP memory uses deposited polysilicon antifuse sandwiches to build its memory cells. The polysilicon based SiO/sub 2/ antifuse show different breakdown characteristics compared to conventional traditional gate oxides. Long-term storage tests show that this 3D-OTP solid-state memory not only can be a general purpose ROM, but also can be an ideal media for archiving.

저온 래디컬 산화법에 의한 고품질 초박막 게이트 산화막의 성장과 이를 이용한 고성능 실리콘-게르마늄 이종구조 CMOS의 제작

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

Electrical reliability of highly reliable 256M-bit mobile DRAM with top-edge round STI and dual gate oxide

A novel CMOS fabrication process with a dual gate oxide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V D=1.8 V. We present a comprehensive study on the I– V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET ( V thn) of between 0.70 and 0.72 V and a saturation current ( I DSAT) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V thn of between 0.85 and 0.90 V and an I DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V g=8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.

Electrical damage of an ultrathin Si oxynitride layer induced by scanning tunneling spectroscopy

Ultrathin Si oxynitride layers were examined by using scanning tunneling microscopy (STM) and spectroscopy (STS). These techniques revealed that a structural change from an intrinsic defect (Si–Si bond) to a damaged structure (Si cluster) takes place under conventional STM/STS conditions. Comparison of the damaged structures formed in the oxynitride with those in the oxide indicated that nitrogen atoms suppress the expansion of the damaged regions. It was also found that nitrogen incorporation enhances both the defect density and the atomic-scale roughness at the oxynitride/Si interface. We suggested that this degradation is related to a local strain produced by the N≡Si3 structures at the oxynitride/Si interface. On the contrary, a normal oxynitride structure had a higher resistance to an electrical stress than an intrinsic defect, but, when the constant electrical stress was applied, the normal oxynitride structure was also damaged. This damage proceeds in two steps: creation of charge traps, and then formation of Si cluster. From these STM/STS results, we proposed that the electrical breakdown of the conventional gate-oxide film proceeds as a four-step process: (1) formation of Si clusters by the damage of intrinsic defects, (2) creation of traps in the normal structure, (3) formation of Si clusters in the normal structure, and (4) complete local breakdown when the Si clusters become connected.