Atomic Layer Deposition of SiN for spacer applications in high-end logic devices

Abstract

Continuous down scaling of transistor size resulted in introduction of high-k material to replace the conventional gate oxide. High-k Metal Gate implementation brings new challenges to the subsequent processing steps of the device. Both oxide ingress and removal of the HKMG stack during later cleaning steps must strictly be avoided. We have developed and optimized an ALD SiN encapsulation liner which protects the HKMG stack and also serves as a robust spacer for subsequent ion implantation. SiN was chosen because of its oxide-blocking characteristics and its durability in diluted hydrofluoric acid. We developed sophisticated ALD processes using ionized ammonia radicals and dichloro-silane. This ALD process has several advantages compared to conventional LPCVD or PECVD processes: Superior thickness control and uniformity, excellent step coverage and no loading effects. In addition, process temperature could be reduced to 500°C, which is shown to be critical for protecting the HKMG stack. Further reduction in process temperature to 400°C is also demonstrated using a novel precursor.