Abstract
For the first time, design, and analysis of vertical gate MOSFET is presented in this paper. This structure consumes significant less area compared to conventional horizontal gate-oxide bulk MOSFET for 7 nm technology generation and onwards. This simple structure also wave offs all complicated fabrication steps needed for formation of gate spacer. The functionality of vertical gate MOSFET or VGMOSFET is found to lie within close proximity to the guidelines of 2013 edition of International Technology Roadmap for Semiconductors or ITRS. All simulation works are done by Sentaurus TCAD software.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
