Conventional Digital Circuits Research Articles

Analysis and Stabilization of Signal Reflections in Gate-to-Gate Connections for AQFP Circuits

Signal integrity of transmitted data is critical for achieving highly dense, large-scale superconductor circuits. Transmission line effects, such as signal reflections, are investigated and concepts from microwave circuit theory and conventional digital logic circuits are applied to AQFP circuits. The lossless transmission line model is used for interconnection modelling. The frequency content and timing characteristics of data signals are used to analytically predict a maximum propagation delay of 6.1 ps before failure due to reflections. This coincides well with our own results, and with those obtained in a separate study using simulation techniques. The investigation then extends towards the design of an impedance matching network with the aim of reducing reflections. The input impedance of a standard buffer gate is derived, and then matched to an 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> transmission line. The proposed impedance matching network maintains data signal integrity up to 3 millimetres. Energy analysis of the matching network is also performed and a 36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> increase in length for similar energy consumption is achieved over alternative solutions.

Graphene barristors for de novo optoelectronics.

Graphene-based vertical Schottky-barrier transistors (SBTs), renowned as graphene barristors, have emerged as a feasible candidate to fundamentally expand the horizon of conventional transistor technology. The remote tunability of graphene's electronic properties could endorse multi-stimuli responsive functionalities for a broad range of electronic and optoelectronic applications of transistors, with the capability of incorporating nanochannel architecture with dramatically reduced footprints from the vertical integrations. In this Feature Article, we provide a comprehensive overview of the progress made in the field of SBTs over the last 10 years, starting from the operating principles, materials evolution, and processing developments. Depending on the types of stimuli such as electrical, optical, and mechanical stresses, various fields of applications from conventional digital logic circuits to sensory technologies are highlighted. Finally, more advanced applications toward beyond-Moore electronics are discussed, featuring recent advancements in neuromorphic devices based on SBTs.

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation

This paper focuses on the design of the conventional CMOS digital circuits and the Multi-Threshold CMOS (MTCMOS) digital circuits, which perform the specific Boolean logic function, as well as the comparison between these designing techniques by their functionality and power consummation (dissipation). The leakage of currents in integrated circuits based on CMOS logic becomes quite significant when the complementary MOS transistors are the small-device geometries (small dimensions), and this effect imposes alternative techniques that enable the designing of CMOS digital circuits with low-power dissipation, even in standby mode. One of these techniques is the design of the CMOS digital circuits with multi-threshold voltage (MTCMOS), which enables the reduction of the leakage power dissipation, as a part of the overall power dissipation in CMOS logic. Two CMOS digital circuits are designed (2-input XNOR CMOS gate and the other one is the CMOS gate that performs a complex Boolean function) based on conventional CMOS technique and multi-threshold voltage CMOS technique, and their functionality and calculation of the average overall power dissipation are tested using the Computer-Aided Design (CAD). The methodology used to achieve low power dissipation in CMOS digital circuits (MTCMOS) will be an efficient method for reducing the overall dissipation, while the high speed performance will be maintained.

One Transistor One Electrolyte-Gated Transistor for Supervised Learning in SNNs

Spiking neural networks (SNNs) are a powerful and efficient information processing approach. However, to deploy SNN on resource-constrained edge systems, compact and low power synapses are required, posing a significant challenge to the conventional silicon-based digital circuits in terms of area- and energy- efficiency. In this study, electrolyte-gated transistors (EGTs) paired with conventional transistors were used as the building blocks to implement SNNs. The one transistor one EGT (1T1E) synapse features heterosynaptic plasticity, which provides a flexible and efficient way to practice supervised learning via spike-timing-dependent plasticity. Based on this method, an SNN with spatiotemporal coding was implemented to recognize the handwritten alphabets, demonstrating 98.3% accuracy at 10% noise level with 5 fJ per synaptic transmission and 1.05 pJ per synaptic programming. These results pave the way for energy-efficiently neuromorphic computing in the future.

Niobium Neuron: RSFQ Based Bio-Inspired Circuit

Neuromorphic and bio-inspired circuits have reached considerable attention since Moore's Law is coming to its limitations. Information processing in mammalian brains takes place in a far more energy-efficient manner and significantly faster than in the best computing architecture nowadays. We propose an approach to bring those benefits to a superconducting information processing circuit. Since the computation in a neuronal network is considered as analogue and the computation as digital, the design is grown around a Josephson comparator with its inherent non-linearity in the transfer function as the central information processing unit. Furthermore, a modified version of the Josephson Transmission Line is used to realize an adaptable coupling between neuron cells. This circuit design benefits of the noise in a 4.2 K environment and is therefore more resilient to noise and switching errors than conventional digital circuits. The proposed circuit behavior in a 2-neuron configuration and the integration in a network topology will be investigated.

Wireless Communications through a Simplified Architecture Based on Time‐Domain Digital Coding Metasurface

AbstractTailoring the electromagnetic responses by metasurface greatly expands one's capabilities to manipulate light in a controlled manner. Either amplitude or phase of the incident wave can be altered during the light–matter interaction, and thus opens the possibility of information modulation without conventional analog or digital circuits. A prototype of quadrature phase‐shift keying (QPSK) wireless communication based on time‐domain digital coding metasurface, whose reflection properties can be varied within different time slots by changing the biasing voltages of varactor diodes in specially designed meta‐atoms, is developed here. As the information is transformed into binary bit streams and mapped to pulse sequences of the biasing voltage, the baseband digital signal is directly modulated to the carrier wave through the digital coding metasurface. Compared to the earlier version of binary frequency‐shift keying architecture based on digital coding metasurface, the proposed QPSK system has a much higher data‐transmission rate for wireless communications. A proof‐of‐concept experiment is conducted to prove the real‐time transmission ability of this system, where a video is delivered between the transmitter and receiver with high accuracy and date rate. The presented work is promising in the development of next‐generation wireless communication technologies.

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs

To mitigate the excess timing margin in conventional digital integrated circuit design, resilient circuits were proposed. The current techniques however either have a large error-detecting register or have difficulty in wide-voltage-range (down to near-threshold) operation. In this paper, we propose a light-weight holosymmetrical transition detector (HTD) that can work reliably at near-threshold to normal VDD with fast response time. Combined with a conventional latch, the HTD-latch is used to replace the end point flip-flop for timing error prediction with an area overhead of only 9.5% over a conventional flip-flop. Besides, we optimize the speculation window and design an adaptive duty-cycle control mechanism to reduce the short-path padding overhead in a resilient circuit. In addition, with voltage scaling, we keep the system working at the point before the first failure by using local detection and global clock gating, which needs neither architectural circuit change nor complicated error recovery mechanism. We apply the above-mentioned three techniques on an eighth-order filter test chip in a 40-nm CMOS process. The measurement results demonstrate that the proposed HTD can work robustly at 0.474–1.1 V. With 4.37% area overhead in total, the proposed resilient technique improves performance by 179.31%/28.2% and energy efficiency by 45.6%/28.1% in a near- $V_{\mathrm {TH}}$ (0.474 V)/super- $V_{\mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins.

Design of hardware RGB to HMMD converter based on reversible logic

Reversible logic computation is one of the most essential promising technologies in designing low-power digital circuits, optical information processing, quantum dot cellular automata, fault tolerant system and nanotechnology. In fact, the conventional digital circuits dissipate a significant amount of energy because several bits of information are deleted during the treatments. In reversible computation, the information bits are not lost. This study presents a novel design of reversible RGB to HMMD converter circuit. The proposed hardware converter is based on several reversible sub-modules as: adder, subtractor, multiplier, register, multiplexer comparator and others. In order to demonstrate the efficiency of the proposed logic design, each sub-module is shown in terms of number of quantum cost needed, gates required delay and garbage outputs produced. Since the works in the field of reversible logic video treatment has only started to bloom, the proposed contribution will engender a new thread of research in the field of reversible real time video treatment.

Novel 8-bit reversible full adder/subtractor using a QCA reversible gate

Conventional digital circuits consume a considerable amount of energy. If bits of information remain during logical operations, power consumption decreases considerably because the data bits in reversible computations are not lost. The types of reversible gate used in quantum computations are quantum-dot cellular automata (QCA), nuclear magnetic resonance, and optical computations. QCA systems offer low power consumption, high density, section regularity and support new devices designed for nanotechnology. A QCA-based reversible gate has minimal delay, complexity and considering the potential quality of a QCA pipeline, computes at maximum speed. The present study designed a novel $$3 \times 3$$3×3 reversible gate that is universal and testable. A reversible logic gate is also designed based on the majority gate in the QCA and as a QCA reversible (QR) gate. A new 8-bit reversible full adder/subtractor based on the QR gate in QCA with a minimum number of cells and area combines both designs for implementation of a reversible full adder/subtractor in QCA. The performance of these gates was compared with testable Fredkin and Toffoli gates and improved performance of logic functions in terms of complexity and delay over those of the Fredkin and Toffoli gates.

Design &amp; Performance Analysis of Low Power Reversible Residue Adder

Reversible logic is a concept of digital circuit design which was invented with the concept of creating digital logic circuits with zero power consumption and minimum power loss. It replaces irreversible logic gates with reversible gates in the conventional digital circuits. Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation .Normal combinational logic circuits dissipate heat for every bit of information lost during their operation. Due to this the recovery of a piece of information once lost is completely impossible. However, if the same circuit is constructed using the reversible logic gates, not only is the recovery possible but also the dissipation of heat reduced. According to Rolf Landauer (1961), whenever we use a logically irreversible gate we dissipate energy into the environment. The loss of information is associated with laws of physics requiring that one bit of information lost dissipates kTln2 of energy, where k is Boltzmann’ constant and T is the temperature of the system. Interest in reversible computation arises from the desire to reduce heat dissipation, thereby allowing [1]: I. Higher densities II. Higher speed Later Bennett, in 1973, showed that this KTln2 joules of energy dissipation in a circuit can be avoided if it is constructed using reversible logic circuits [2]. According to Moore’s law, the number of chip components doubling every 18 months, the irreversible technologies would dissipate a lot of heat and heat reduces circuit life. Reversible logic not only recovers the lost information but also dissipate less heat. A Reversible Logic Gate is an n-input, n-output device with One-to-One Mapping, which helps in determining the outputs from the inputs and vice versa. An important On lin e V ers ion O nly .

4.2 GHz 0.81 mW triple‐modulus prescaler based on true single‐phase clock

A dual-modulus prescaler based on true single-phase clock D flip-flop is presented. Instead of using the conventional digital logic circuit, the pass transistor logic circuit is applied to reduce the number of the transistors and the power of the divider. By adding only two additional transistors, a dual-modulus operation is achieved. Implemented in a standard 180 nm CMOS process, the proposed divide-by 6/7/8 prescaler based on the proposed dual-modulus one achieves an operating frequency of 4.2 GHz with a measured power consumption of 0.81 mW for a 1.2 V supply.

Parallel database search and prime factorization with magnonic holographic memory devices

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.

Accelerated Aging in Analog and Digital Circuits With Feedback

Aging mechanisms such as Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) are key limiting factors of circuit lifetime in CMOS design. Threshold voltage shift of a device due to degradation is usually a gradual process, only causing moderate increase in failure rate of CMOS designs. Conventional analog and digital circuits typically employ feedback control for system stability or Dynamic Voltage Scaling (DVS) to optimize power performance respectively. For such closed loop topologies, the degradation rate can be dramatically accelerated, leading to destructive consequences. To identify such catastrophic phenomenon, this work (1) presents accurate simulation framework and aging models for BTI and CHC accounting underlying physics. Complete methodology is validated with 28 nm and 65 nm silicon data. (2) Investigates Bias Runaway, a rapid increase of gate-drain voltage of a bias circuit in analog/mixed signal (AMS) circuits. Along with silicon evidence, critical boundary condition and design trade-offs for bias runaway are also explored with technology scaling. (3) DVS induced acceleration in failure rate of logic circuits under NBTI and PBTI is demonstrated. Overall, this work identifies key issues to the stability of feedback systems, which is vitally important for reliable IC designs.

All-Optical Reversible Network Design Using Microring Resonators

Conventional digital circuits cannot be run in reverse direction and the bits of information are destroyed during the operation. Reversible computation is a research area characterized by only computational models of both forward and backward deterministic. In this paper, reversible network architectures using all-optical Si microring resonators have been proposed. Mathematical models and numerical simulated results have been performed to finding the performance of the network architecture. Transformation matrix calculations and quantum realization using SWAP gates for (k, k) reversible networks are also given in this paper.

Behavior of stochastic circuits under severe error conditions

Abstract Stochastic computing is an old and unconventional computing technique that is finding promising new applications in image processing and the handling of complex error-correcting codes. Stochastic circuits offer an alternative to conventional digital circuits because of their extremely small size and inherent noise tolerance. They are also well-suited to meeting the requirements of emerging nanoscale technologies where non-deterministic behavior due to manufacturing defects and soft errors cannot be ignored. Error analysis of stochastic circuits, however, has received little attention and remains a largely open problem, especially when multiple errors affecting both the data sources and the stochastic circuits can occur in the course of a computation. This paper attempts to analyze stochastic circuits under various error conditions, and to compare their behavior to that of conventional circuits under similar error conditions. We use probabilistic transfer matrices for this analysis, complemented by circuit simulation. Our results indicate that stochastic circuits provide significantly better error tolerance under severe error conditions.

All-Optical Modified Fredkin Gate

Conventional digital circuits lose energy because the bits of information are destroyed during the operation. Reversible circuits are currently on the top approaches to power minimization with its application in all-optical-based systems. Fredkin gate is a very common reversible logic gate. In this paper, a modification of the Fredkin gate is proposed. All-optical circuit of this modified Fredkin gate (MFG) is also designed using semiconductor optical amplifier on the Mach-Zehnder interferometer switch. A 16-Boolean logical operational circuit is also shown using this MFG. The main advantage of this scheme is that we can design a 15-Boolean logical function using a single MFG unit. Only one operation (nand) required two MFG units. Hence, complexity of the circuit can be reduced. Also, multivalued T-gate circuit using MFG is proposed.

Intelligent Robot with Microcontroller for Obstacles Avoiding

The paper describes a intelligent robot with two stepper motor and microcontroller PIC16F84A for obstacles avoiding (IRSMP). An experimental prototype, based on a stepper motor, microcontroller PIC16F84A and infrared sensors, has been realized using conventional digital circuits. The proposed control scheme can be usefully applied to any intelligent robot. The infrared sensors has using for obstacles avoiding. The program for microcontroller is making in assembler language.

CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits

CMOS circuits consume great dynamic power in switching. It has been proposed that energy transfer through a rising Vdd dissipates small amounts of energy. In typical power gate circuits, the high-performance PMOS transistors (PSW) that connect the circuit blocks to the power supply reduce leakage power by shutting off outer power (Vdd) to the idle blocks. We expand this technique by utilizing active PSW, which are turned on and off by clock signal. The PSW are fully turned on only for half of each clock cycle. This means that sufficient Vdd is provided to the circuit continuously for half of each clock cycle. In this manner, the circuit charge and discharge actions are cycle occur in different phases, and ramp Vdd is supplied to the designed circuit; we name this technique “CKVdd.” CKVdd is a clock-controlled self-stabilized voltage technique, which generates stable ramp voltage to suppress the currents effectively. It is proposed to reduce dynamic power dissipation in conventional CMOS digital circuits. As compared to the conventional circuit, the circuits using CKVdd technique possesses several characteristics that differ from those of the current circuits using constant Vdd power source. First, CKVdd technique combines the power source and clock signal; it is an efficient low power technique. Second, CKVdd propose a feasible method to generate ramp-Vdd and low-Vdd. This technique would be convenient used to design generic low power digital circuits. Third, normal CMOS circuits show the dynamic power consumption increase proportional to the clock frequency. CKVdd results in a lower-than-usual frequency dependency, it is suitable used to design high clock speed circuits. In investigating constant Vdd for MPEG VLD decoders, CKVdd-circuit reduces 48% of the usual power dissipation and 88% of the usual peak current with small delay penalty.

Reversible-Logic Design With Online Testability

Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

A low-jitter mixed-mode DLL for high-speed DRAM applications

This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-/spl mu/m triple-metal CMOS process and occupies a die area of 0.45 mm/sup 2/. Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply.