Abstract
Aging mechanisms such as Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) are key limiting factors of circuit lifetime in CMOS design. Threshold voltage shift of a device due to degradation is usually a gradual process, only causing moderate increase in failure rate of CMOS designs. Conventional analog and digital circuits typically employ feedback control for system stability or Dynamic Voltage Scaling (DVS) to optimize power performance respectively. For such closed loop topologies, the degradation rate can be dramatically accelerated, leading to destructive consequences. To identify such catastrophic phenomenon, this work (1) presents accurate simulation framework and aging models for BTI and CHC accounting underlying physics. Complete methodology is validated with 28 nm and 65 nm silicon data. (2) Investigates Bias Runaway, a rapid increase of gate-drain voltage of a bias circuit in analog/mixed signal (AMS) circuits. Along with silicon evidence, critical boundary condition and design trade-offs for bias runaway are also explored with technology scaling. (3) DVS induced acceleration in failure rate of logic circuits under NBTI and PBTI is demonstrated. Overall, this work identifies key issues to the stability of feedback systems, which is vitally important for reliable IC designs.
Published Version
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