Conventional CMOS Process Research Articles

Work function tuning of metal nitride electrodes for advanced CMOS devices

A novel method for tuning the work function of metal nitride (MN x ) metal gates by incorporating lanthanide elements into MN x is demonstrated for application in nMOSFETs. The work function ( Φ M) of MN x metal gates, such as TaN and HfN, can be tuned continuously down to 4.2–4.3 eV even after rapid thermal annealing (RTA) up to 1000 °C by incorporating lanthanide elements, such as terbium (Tb), erbium (Er), or ytterbium (Yb), into MN x gates. In addition, the lanthanide-MN x metal gates exhibit good thermal stability on both SiO 2 and HfAlO high-κ dielectrics in terms of equivalent oxide thickness (EOT) and leakage current, making them promising metal gate candidates in the conventional self-align bulk-Si CMOS process flow. The effect of N in lanthanide-MN x is also studied and the results show that the enhanced nitrogen content in lanthanide-MN x could be of importance for the thermal stability as well as other properties of MN x .

Silicon nanocrystal-based non-volatile memory devices

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 °C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide).

Thick Oxide Layer Fabrication Process for Silicon RF ICs

We present a new method to reduce substrate losses and parasitic capacitances of passive elements on silicon RF ICs. The method is based on a fabrication process to selectively bury thick oxide layer regions in a silicon substrate. The process consists of two steps, such as high aspect-ratio trench forming using a D-RIE (Deep Reactive Ion Etching) technique, high temperature oxidation in a wet environment, polycrystalline silicon deposition and etching. This is also CMOS compatible one.Using the method, we have succeeded in fabrication of 25μm thick oxide layer regions in a silicon substrate. The maximum Q value of a spiral inductor on the thick oxide layer has been improved twice as large as one on a field oxide layer fabricated by a conventional CMOS process. In addition, the power consumption of a 1.6GHz VCO (Voltage Controlled Oscillator) using the spiral inductor on the thick oxide layer has been reduced by 40% compared with the one by conventional technologies.

Ultrathin HfO[sub 2](EOT<0.75 nm) Gate Stack with TaN∕HfN Electrodes Fabricated Using a High-Temperature Process

With the continuous scaling of the complementary metal oxide semiconductor CMOS technology, high-k gate dielectrics will be needed to replace conventional SiO2 gate dielectrics for addressing the excessive high leakage concern. 1 HfO2 has been considered as one of the most promising candidates for such applications. 2 Much effort has been made in developing a HfO2 gate stack with equivalent oxide thickness EOT of less than 1 nm. 3-7 Although the asdeposited HfO2-based gate dielectrics with metal gate electrode could achieve an EOT 1 nm, a significant increase of both the EOT and the leakage current have been reported after the gate stack has been subjected to high temperature postmetallization annealing PMA. 3-6 The increase of EOT during PMA has been speculated to be caused by either the reaction at the metal gate/HfO2 interface and/or the poor oxygen diffusion barrier of the metal gate electrode. This thermal instability is a major concern for conventional gatefirst CMOS processing. In this article, we have demonstrated a high-quality HfO2 gate stack fabricated using NH3-based surface nitridation prior to HfO2 deposition in order to suppress interfacial oxidation at the HfO2/Si interface as well as the HfN gate electrode that has been shown to be an excellent oxygen diffusion barrier.

Analysis on the effect of parallel current path on the quality factor of CMOS spiral inductors for 1–10 GHz

A structure of spiral inductor having a parallel current path through the branch of the metal strip was designed to achieve a quality ( Q) factor enhancement compatible with conventional CMOS and/or established SiGe process in RF and microwave arena. The Q factor enhanced by 12% was quantitatively analyzed with a lumped-element model and its origin was investigated at a structural point of view. As a result we noted that the parallel-branching structure greatly reduced the series resistance of the inductor at a high frequency range of GHz by suppressing current crowding and in turn enhanced the Q factor beyond the additional parasitic capacitance.

Heterodimensional FET With Split Drain

A modification to heterodimensional field effect transistors (HDFET) is introduced and demonstrated to provide novel switching capabilities. The modification consists of introducing a split drain into the HDFET structure allowing the transistor to operate as a single pole-double throw switch. By extension, multiple pole-multiple throw switches can be made within a single transistor structure by introduction of multiple split drains or sources. If the device is fabricated on silicon germanium substrates, compatibility of the structure with conventional CMOS processing is achievable, allowing for new applications in digital, mixed signal, and high voltage switching.

Stability of Co/Ni Silicide in Metal Contact Dry Etch

Newly developed silicide materials for ULSI should have the appropriate electrical property of low resistant as well as process compatibility in conventional CMOS process. We prepared silicides from 15 nm-Co/15 nm-Ni/Si structure and performed contact dry etch process to confirm the dry etch stability and compatibility of layers. We dry etched the photoresist/SiO/silicide/silicon patterns with gases with varying powers from 100 to 200 W, and pressures from 45 to 65 mTorr, respectively. Polysilicon and silicon active layers without silicide were etched during over etch time of 3min, while silicon layers with proposed silicide were not etched and showed stable surfaces. Our result implies that new silicides may replace the conventional silicides due to contact etch process compatibility.

Design, fabrication and characterisation of strained Si∕SiGe MOS transistors

Strained Si/SiGe heterostructure MOS transistors offer great promise for nanoscale CMOS technology. This paper reviews these high performance devices and the challenges associated with their integration into conventional CMOS processes. Simulation results at a device and circuit level show that n-channel MOSFET performance can influence circuit speed to a greater extent than p-channel devices. Consequently the experimental work discussed is focused on recent progress in the optimisation of strained Si/SiGe n-channel MOSFETs. Simulation predicts that dual channel CMOS architectures offer the greatest performance advantages for both n- and p-channel MOSFETs. However, experimental evidence suggests that a single channel CMOS architecture may be a more pragmatic choice, given the material and processing complexities involved. The optimum SiGe alloy composition for virtual substrate based devices is discussed. Electron mobility is shown to peak in strained Si channels fabricated on relaxed Si0.75Ge0.25, yet wafer yield is compromised for virtual substrate compositions incorporating Ge contents above 15%. Optimum strained Si/SiGe device design is therefore shown to be highly dependent on the device parameter to be optimised, and specific processing conditions.

SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge-Condensation Technique for High-Mobility Channel CMOS Devices

ABSTRACTA new fabrication method of SiGe-on-Insulator (SGOI) and Ge-on-Insulator (GOI) structures are presented as well as the application to high-mobility channel CMOS devices. This method, the Ge-condensation technique, consists of epitaxial growth of a SiGe layer with a low Ge fraction on an SOI substrate and successive oxidation at high temperatures, which can be incorporated in conventional CMOS processes. During the oxidation, Ge atoms are pushed out from the oxide layer and condensed in the remaining SiGe layer. The interface between the Si and SiGe layers is disappeared due to the interdiffusion of Si and Ge atoms. Eventually, an SGOI layer with a higher Ge fraction is formed on the buried oxide layer. The Ge fraction in the SGOI layer can be controlled by the oxidation time because total amount of Ge atoms in the SGOI layer is conserved throughout the oxidation process. We found that the lattice relaxation in the SGOI layer also can be controlled through the initial SiGe thickness. P- and n-type strained SOI MOSFETs, which were fabricated on relaxed SGOI substrates formed by this technique, exhibited mobility enhancement of 50% and 80%, respectively. CMOS ring oscillators comprised of the MOSFETs exhibited reduction in propagation delay of 70%-30% compared to a conventional SOI-CMOS device. Ultrathin-body strained SGOI pMOSFETs with high Ge fraction and surface channels were also fabricated by this technique. These devices exhibited hole-mobility enhancement factors up to 2.3. Furthermore, Ge-on-Insulator (GOI) structures with thicknesses less than 10 nm were realized for ultrathin body GOI-CMOS applications by using the Ge-condensation technique. In conclusion, the Ge-condensation technique is a promising technique for fabricating various types of high-mobility channel-on-insulator devices.

Low leakage and high performance of nMOSFET using SiGe layer as a diffusion barrier

As a boron diffusion barrier, a 20 nm-thick Si 0.8Ge 0.2 layer was successfully utilized in n-channel MOSFETs for implementing a retrograded well structure. Compared with the conventional Si CMOS process, the developed n-channel MOSFET process provides an enhanced transconductance (7%) and lower sub-threshold swing which is nearly unchanged even at an increased drain-source voltage. Especially, because sub-threshold leakage current is one of the key issues in the MOS device scaling due to reduced threshold voltage, the usage of a Si 0.8Ge 0.2 layer in n-channel MOSFET was verified to be useful for low power and high performance even under aggressive scaling constraints.

Actively recharged single photon counting avalanche photodiode integrated in an industrial CMOS process

Abstract An actively recharged single photon counting avalanche photodiode (SPAD) is integrated in a conventional CMOS process. A fast recharge through a low impedance path leads to a dead time lower than 10 ns. This outstanding feature allows one to work with pulse repetition rate up to 100 MHz in time correlated single photon counting based experiments. Biased 2.5 V above its breakdown voltage, the 30 μm 2 sensitive area photodiode has a maximum detection probability of about 20% at λ =440 nm and up to 5% in the visible part of the spectrum. At this bias condition, the dark count rate is as low as 60 Hz at room temperature, making a cooling of the microsystem unnecessary. The AR-SPAD exhibits no afterpulsing phenomenon revealing the maturity of the CMOS process used. The timing resolution of the AR-SPAD is less than 50 ps. For applications where the photons can be focused on the detector with an objective, the AR-SPAD is highly competitive with commercially available single photon counter. Furthermore, CMOS integration opens the way to arrays fabrication as well as co-integration of additional functions to develop smart optical sensors.

A CMOS-MEMS mirror with curled-hinge comb drives

A micromirror achieves up to ±4.7° angular displacement with 18 Vdc by a comb-drive design that uses vertical angled offset of the comb fingers. Structures are made from a combination of CMOS interconnect layers and a thick underlying silicon layer. Electrical isolation of the silicon fingers is realized with a slight silicon undercut etch, which disconnects sufficiently narrow pieces of silicon under the CMOS microstructures. The 1 mm by 1 mm micromirror is made of an approximately 40 μm-thick single-crystal silicon plate coated with aluminum from the CMOS interconnect stack. The mirror has a peak-to-peak curling of 0.5 μm. Fabrication starts with a conventional CMOS process followed by dry-etch micromachining steps. There is no need for wafer bonding and accurate front-to-backside alignment. Such capability has potential applications in biomedical imaging, optical switches, optical scanners, interferometric systems, and vibratory gyroscopes.

Epitaxial praseodymium oxide: a new high- K dielectric

We show results for molecular beam epitaxial growth of praseodymium oxide on Si. On Si(1 0 0) oriented surfaces, crystalline Pr 2O 3 grows as (1 1 0)-domains, with two orthogonal in-plane orientations. Epitaxial overgrowth with Si could not been realized so far. We obtain perfect epitaxial growth of hexagonal Pr 2O 3 on Si(1 1 1). These layers can also be overgrown epitaxially with Si leading to novel tunnel structures. Crystalline Pr 2O 3 on Si(0 0 1) is a promising candidate for highly scaled gate insulators, displaying sufficiently high- K value of around 30, ultra-low leakage current density, good reliability, and high electrical breakdown voltage. The Pr 2O 3/Si(0 0 1) interface exhibits the symmetric band alignment, desired for applying such material in both n- and p-type devices. The valence band as well as the conduction band offset to Si is above 1 eV. The electron masses can be assumed to be very heavy in the oxide. This effect together with the suitable band offsets leads to the unusually low leakage currents found experimentally. Finally, the integration of crystalline Pr 2O 3 high- K gate dielectrics into a conventional CMOS process will be demonstrated.

Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

AbstractTo facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

A Study to Determine an Effective Ground-Shield Structure for a Silicon On-Chip Spiral Inductor

This paper describes a study to improve the quality factor (Q-factor) of a silicon-on-chip spiral inductor by determining the most appropriate shape and structure of inductor wires and a ground shield. Electro-magnetic field simulation is carried out under the condition that the spiral inductor is formed on a P-substrate with an electric conductivity of 10 [Ω -1 m -1 ] in assuming the use of a conventional CMOS process. After assessing the simulation results, we propose a new, ring-type structure for the wires and a comb-shaped ground shield that is placed under the inductor wires only. This comb-like shape reduces the stray capacitance between the shield and the inductor wires. As the Q-factor value of a spiral inductor depends on the distance between the ground shield and the inductor wires, as well as on the resistivity of the ground shield material, those influences are also clarified. As a result, we obtain 15% to 23% increases in the Q-factor values in the frequency range of 2 to 3.5 GHz for a 7 nH inductor. We also identify a material possessing the appropriate resistivity to serve as a ground shield.

Suppression of boron TED by low temperature SPC anneal prior to dopant activation

The application of a low temperature solid phase crystallization (SPC) anneal to nonpreamorphized junctions prior to a high-temperature dopant activation anneal is proposed. The SPC anneal eliminates implantation-induced defects which give rise to transient enhanced diffusion (TED), and thus reduce both vertical and lateral boron diffusion by 16 nm and 24 nm, respectively, in a conventional CMOS process thermal budget. Improved short channel effect (SCE) immunity was demonstrated with sub-100 nm FETs.

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.

Low-noise silicon avalanche photodiodes fabricated in conventional CMOS technologies

We present a simple design technique that allows the fabrication of UV/blue-selective avalanche photodiodes in a conventional CMOS process. The photodiodes are fabricated in a twin tub 0.8 /spl mu/m CMOS technology. An efficient guard-ring structure is created using the lateral diffusion of two n-well regions separated by a gap of 0.6 /spl mu/m. When operated at a multiplication gain of 20, our photodiodes achieve a very low dark current of only 400 pA/mm/sup 2/, an excess noise factor F=7 at /spl lambda/=400 nm and a good gain uniformity. At zero bias voltage, the responsivity peaks at /spl lambda/=470 nm, with 180 mA/W. It corresponds to a 50% quantum efficiency. Successive process steps are simulated to provide a comprehensive understanding of this technique.

Drift region optimization of lateral RESURF devices

High-voltage lateral devices commonly uses the RESURF concept to achieve a high breakdown voltage. This however limits the conducting performance in the drift region due to the drift region charge that is determined by the RESURF criteria. This paper shows a method to overcome this limitation without effecting the breakdown voltage. The concept is to create a dual conducting device by introducing two extra layers in the drift region. Using the proposed method shows that the drift region resistance can be reduced with a factor 2 without significant reduction of the breakdown voltage. The substrate used is a CMOS substrate which makes it possible to use this concept in a conventional CMOS process.

Epitaxial Praseodymium Oxide: A New High-K Dielectric

ABSTRACTWe show results for molecular beam epitaxial (MBE) growth of praseodymium oxide on Si. On Si(100) oriented surfaces, crystalline Pr2O3 grows as (110)-domains, with two orthogonal in-plane orientations. Epitaxial overgrowth with Si could not been realized so far. We obtain perfect epitaxial growth of hexagonal Pr2O3 on Si(111). These layers can also be overgrown epitaxially with Si leading to novel tunnel structures. Crystalline Pr2O3 on Si(OOl) is a promising candidate for highly scaled gate insulators, displaying sufficiently high-K value of around 30, ultra-low leakage current density, good reliability, and high electrical breakdown voltage. The Pr2O3/Si(001) interface exhibits the symmetric band alignment, desired for applying such material in both n- and p-type devices. The valence band as well as the conduction band offset to Si is above 1 eV. The electron masses can be assumed to be very heavy in the oxide. This effect together with the suitable band offsets leads to the unusually low leakage currents found experimentally. Finally, the integration of crystalline Pr2O3 high-K gate dielectrics into a conventional CMOS process will be demonstrated.