Ultrathin HfO[sub 2](EOT<0.75 nm) Gate Stack with TaN∕HfN Electrodes Fabricated Using a High-Temperature Process

Abstract

With the continuous scaling of the complementary metal oxide semiconductor CMOS technology, high-k gate dielectrics will be needed to replace conventional SiO2 gate dielectrics for addressing the excessive high leakage concern. 1 HfO2 has been considered as one of the most promising candidates for such applications. 2 Much effort has been made in developing a HfO2 gate stack with equivalent oxide thickness EOT of less than 1 nm. 3-7 Although the asdeposited HfO2-based gate dielectrics with metal gate electrode could achieve an EOT 1 nm, a significant increase of both the EOT and the leakage current have been reported after the gate stack has been subjected to high temperature postmetallization annealing PMA. 3-6 The increase of EOT during PMA has been speculated to be caused by either the reaction at the metal gate/HfO2 interface and/or the poor oxygen diffusion barrier of the metal gate electrode. This thermal instability is a major concern for conventional gatefirst CMOS processing. In this article, we have demonstrated a high-quality HfO2 gate stack fabricated using NH3-based surface nitridation prior to HfO2 deposition in order to suppress interfacial oxidation at the HfO2/Si interface as well as the HfN gate electrode that has been shown to be an excellent oxygen diffusion barrier.