Conventional Carry Select Adder Research Articles

Performance Analysis of 8-Bit Carry Select Adder

In this study, we evaluated the performance of an 8-bit carry-select adder (CSA) implemented through transmission gates for various metrics such as speed and area. Adders are an important part of digital computer systems and are used to perform additional operations. CSA is a well-known adder type known for its fast performance. Our results suggest that CSA implemented using transmission gates may improve the performance of digital circuits by achieving faster performance due to the low resistance and fast switching properties of these gates. In addition, we also analyzed the area utilization of CSA by measuring the number of transistors in the synthesized design. The integration of transmission gates into the CSA can affect area characteristics and our analysis provides insight into the design's area efficiency. CSA was developed in this study using transmission gate technology along with MTCMOS D-latch to achieve superior performance compared to previous studies. Simulations were performed using 250nm CMOS technology from Tanner and Mentor Graphics. His CSA implementation with transmission gate logic significantly reduced transistor count by 58.85% compared to his conventional CSA. This approach was chosen for its better results and improved overall performance.

Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

In every modern ICs the adders are essential components. Adder’s performance has a substantial impact on the architecture of signal processing, controller, the module of filter, the module of data storage, etc., high-speed and area-efficient circuits are the most substantial parameters in every modern integrated circuit. Carry select adder operates at high speed, but it consumes more power due to the large area. The present approach discloses different VLSI hybrid carry select adder architectures. The hybrid technology-based Carry Select adder (CSELA) consists of two stages, namely the Hancarlson adder stage and Hybrid Stage is proposed. In this technique, all the stages (4 bits in each stage) are performed simultaneously to improve the speed and area further. The propagation delays of the proposed adder are the summation of two full adders, seven Multiplexers (4:1) and BEC(3 bit) for producing Cout. The proposed work indicates that the hybrid carry select adder operates at high a speed with a lesser area than the conventional adder. The proposed design is simulated and synthesized in Xilinx ISE 12.1 using Verilog HDL with a family of Vertex6 FPGA devices (Device No. XC6VLX75T, Package FF484, Speed -3). The synthesized report shows that the speed of the proposed adder is improved by 49.06%, 52.61%, 47.58%, 19.08%, 39.9%, 1.25%, 44.43%,19.08%, 44.07% and 71.59% compared to RCA, CBL-based CSELA, CLA, Weinberger BEC-based CSELA,D latched CSELA, Brent Kung CSELA, Brent Kung RCA-based CSELA, CSA Weinberger, Conventional CSELA and Ling CSELA, respectively.

An error efficient and low complexity approximate multi‐bit adder for image processing applications

SummaryApproximate computing‐based hardware is directed towards reduction in area and power consumption; it finds better suitability in various image processing applications. In order to achieve low complexity, approximate techniques are applied in the arithmetic units which provide promising results in enhancing the performance of DSP processors with optimal degradation on its accuracy. In this paper, two approximate full adder designs are proposed, namely, the first design as proposed approximate full adder 1 (PAA1) and the second design as proposed approximate full adder 2 (PAA2). In both the designs, the approximation on the Boolean expressions is carried out to reduce the hardware complexity with the significant tolerance on the error rate. Also, a multi‐bit approximate carry select adder is proposed with the utilization of PAA1 and PAA2, respectively. The performance of the proposed adders is analyzed in terms of parameters like gate count, structural synthesis, error, and also in terms of image metrics. The proposed and existing designs are synthesized using Synopsys Design Compiler with TSMC 65 nm technology for better comparison. Synthesis results indicate that the proposed 16‐bit approximate carry select adder (CSLA) shows a significant reduction of 58% in area delay product and 70% in power delay product, in comparison with the conventional CSLA. The image metrics results also validate that the proposed adder with highest peak signal‐to‐noise ratio is highly adoptable for image processing applications.

Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder

Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.

FPGA Implementation of High Speed Hardware Efficient Carry Select Adder

This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.

Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

High Speed Error Tolerant Adder for Multimedia Applications

In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.

Design of Vedic Multiplier Using SQRT Carry Select Adder (CSLA)

Vedic multiplier is designed using area-efficient Carry Select Adder (CSLA). As the multiplication is the process of subsequent addition, adder is important block in implementation of multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead of simple Ripple Carry Adder (RCA). Carry select adder is known to be one of the fastest adder structures. Here Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. The goal is to design Vedic multiplier based on crosswise and vertical algorithms using area efficient Sqrt CSLA. Conventional CSLA designs like Binary to Excess one Converter (BEC) based CSLA and Modified CSLA (MCSLA) are compared with proposed CSLA design to prove its efficiency. It shows improved performance in terms of area. This renovated CSLA is used to design proposed Vedic multiplier. The proposed Sqrt CSLA based Vedic multiplier provides better results in power and speed of the digital circuits.

Energy Efficient BEC Modified Carry Select Adder Based PTMAC Architecture for Biomedical Processors

AbstractPower dissipation is considered as the critical objective in the design of integrated circuits. Concern has increased in the design of adders, which form the basic computational block of any circuit. Research work has been carried out towards the efficient design and performance analysis of Carry Select Adder. Carry Select Adder (CSLA) is used in many data processors to increase the speed of mathematical calculation. The main aim of this paper is to reduce the power by using Binary to Excess-1 Converter, which uses an uncomplicated and proficient gate-level adaptation to reduce the power and area of the Carry Select Adder to a tolerant level. Based on the analysis, the proposed design proves to be better than the Conventional CSLA, BEC Modified Carry Select Adder and the Regular Square Root CSLA. Moreover, the Programmable Truncated Multiplier and Accumulator Circuit architecture designed using the BEC modified CSLA can be used for low power biomedical instrumentation with a need for reticent digi...

128-Bit Area Efficient Reconfigurable Carry Select Adder

Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and compared with the conventional CSLA architecture. The proposed design greatly reduces the area compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the proposed design, the conventional CSLA has 65.80% less area.

High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications

Addition is one of the fundamental arithmetic operations which are used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. In this paper, the Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) is constructed, which is efficient in terms of accuracy, power and area. While considering the elementary structure of an image processing applications, it is a combination of the multipliers and delays, which in turn are the combination of the adders. This research paper describes the Algorithmic strength reduction technique which leads to a reduction in hardware complexity by exploiting the significances. This transformation is basically implemented for the reduction in the power consumption and area efficient of Very Large Scale Integration (VLSI) design or iteration period in a programmable Digital Signal Processing (DSP) implementation. The significance approximation error tolerant adder is designed using full adder and approximate full adder cells with reduced complexity at the gate level. The performance of 16 bit conventional Carry Select Adder (CSLA), 16 bit Error Tolerant carry select Adder (ET-CSLA) and proposed Significance Approximation Error Tolerant Carry Select Adder (SAET-CSLA) are compared. For all the 216 input combinations, comparison is made between existing and proposed CSLA adders and the error tolerance analysis is carried out for accuracy improvement. Application of image processing is carried out using proposed SAET-CSLA.

Low Power, Area Efficient & HighPerformance Carry Select Adder on FPGA

LOW-POWER, area-efficient, and high-performance VLSI systems are increasingly used in portable and mobile devices, multi standard wireless receivers, and biomedical instrumentation. An adder is the main component of an arithmetic unit. A complex digital signal processing (DSP) system involves several adders. An efficient adder design essentially improves the performance of a complex DSP system. A ripple carry adder (RCA) uses a simple design, but carry propagation delay (CPD) is the main concern in this adder. Carry look-ahead and carry select (CS) methods have been suggested to reduce the CPD of adders. A conventional carry select adder (CSLA) is an RCA configuration that generates a pair of sum words and output carry bits corresponding the anticipated input-carry (cin = 0 and 1) and selects one out of each pair for final-sum and final output-carry . A conventional CSLA has less CPD than an RCA, but the design is not attractive since it uses a dual RCA. In the existing designs, logic is optimized without giving any consideration to the data dependence. In this paper, we prepared an analysis on logic operations occupied in conventional and BEC-based CSLAs to study the data dependence and to identify redundant logic operations. Based on this study, we have planned a new logic formulation for the CSLA. The major contribution in this paper is logic formulation based on data dependence and optimized carry generator (CG) and carry select unit Based on the proposed logic formulation, we have found a capable logic design for CSLA. Due to better logic units, the projected CSLA involves significantly less ADP than the existing CSLAs. We have shown that the SQRT-CSLA using the proposed CSLA design involves nearly 32% less ADP than that of the corresponding SQRT-CSLA.

Low Power, Area-Efficient and High Speed Fast Adder for Processing Element

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate - level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Modified Carry select adder (MCSLA), Regular Square Root CSLA (SQRT CSLA), Modified SQRT CSLA and Proposed SQRT CSLA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the conventional CSLA.

English

Carry SeLect Adder (CSLA) is known to be the fastest adder among the Conventional adder structures. Carry select adders provides a good compromise between cost, area and performance among carry propagation adders. Due to its less complex structure, there is still scope for obtaining better design Carry SeLect Adder (CSLA) architecture designs for power optimization combined with better performance. The conventional CSLA architecture uses dual RCAs which has large area consuming.Proposed technique eliminates all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the Carry Select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. Due to its small carry-output delay,the proposed CSLA design is a good candidate for SQuare-RooT (SQRT) CSLA.

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.

Area–Delay–Power Efficient Carry-Select Adder

In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of-final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to c <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> = 0 and 1) and fixed c <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area-delay-product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths.

Low Power High Speed SQRT Carry Select Adder

Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder among other. There is scope to reduce the power consumption in the regular CSLA. A simple gate level modification is required of the regular CSLA to reduce the power. This paper proposes modified 40-bit square-root CSLA (SQRT CSLA) architecture. Both the regular and modified 40-bit CSLA are designed with TSMC 0.13-µm CMOS process technology and results are compared with TSMC 0.18-µm CMOS process technology. The proposed design has reduced area and power as compared with the regular SQRT CSLA withy slight increase in the delay. The result analysis shows that proposed CSLA has better performance than conventional CSLA.

64-bit carry-select adder with reduced area

A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder.

Completion-detecting carry select addition

Logic analysis, circuit implementation and verification of a novel self-timed adder scheme based on carry select (CS) logic are presented. The preliminary analysis of the variable-time behaviour of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimise the average performance. The logic design and full-custom circuit implementation is described of a completion-detecting CS adder by means of precharged CMOS logic. The correct asynchronous operation of the circuit is verified by means of layout level SPICE simulation referring to a 0.35 μm CMOS process. The worst-case addition time is comparable with the fastest fixed-time adders, which is a considerable result for a completion-detecting technique. The hardware overhead can be limited to 23% over a conventional CS adder. SPICE simulation estimates an average detected addition time of 1.6 ns for a 64 bit adder, including the precharge time.