An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

Abstract

Abstract To choose the option between an excess-1 result and a normal result,
the conventional carry select adder (CCSA) employs two ripple-carry adders and a
multiplexer in the last step. Second, whereas the proposed single-stage carry select
adder (SSCSA) avoids using full adders for the generation of both normal and excess
results, the present full adders require multiple full adders. A novel architecture is
developed and specifically designed to improve power dissipation and latency. It relies
on a single circuit that produces normal/excess-1 results dependent on input carry.
Heterogeneous logic combining CMOS, Dual Value Logic (DVAL), and Transmission
Gate Logic (TRGL) with 22nm Fin-FETs powers the 1-bit SSCSA circuit. Better
circuit regularity is displayed by the 4-bit SSCSA as it only uses one type of 1-bit
SSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22nm FinFET
technology, all adders, including 4- and 8-bit adders, are designed, simulated, and
examined. According to the resulting study, the 4-bit SSCSA outperforms the best
adder currently in use in terms of speed performance and power dissipation by 17.6%
and 27.6%, respectively. By comparison with all other designs, SSCSAs outperform
them at each and every corner.