Low Power High Speed SQRT Carry Select Adder

Abstract

Design of high speed and low power data path logic systems are one of the most challenging areas of research in VLSI system design. Adder circuit is the main building block in DSP processor. However, Digital adders suffer with the problem of carry propagation delay. To alleviate this problem Carry Select Adder (CSLA) are used in computational unit. Carry Select Adder one of the fastest adder among other. There is scope to reduce the power consumption in the regular CSLA. A simple gate level modification is required of the regular CSLA to reduce the power. This paper proposes modified 40-bit square-root CSLA (SQRT CSLA) architecture. Both the regular and modified 40-bit CSLA are designed with TSMC 0.13-µm CMOS process technology and results are compared with TSMC 0.18-µm CMOS process technology. The proposed design has reduced area and power as compared with the regular SQRT CSLA withy slight increase in the delay. The result analysis shows that proposed CSLA has better performance than conventional CSLA.