Conventional 6T SRAM Cell Research Articles

Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells

Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate oxide breakdown on the performance of a conventional 6T SRAM cell is presented for 45-nm predictive technology. The DC margins (read, write, and retention) and access times (read and write) during wearout are analyzed, and a cell breakdown point due to degradation in each of these parameters is defined. A combination of these results is used to formulate a definition for the hard-breakdown point of a cell. An on-chip process, voltage, and temperature tolerant monitoring scheme is proposed to detect the gradual wearout of SRAM cells. The monitoring scheme enables the detection of impending cell failure, which in turn can trigger reconfiguration of the SRAM with redundant rows and/or columns prior to failure.

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

Abstract. The conventional sensing scheme of single-ended read-only-ports as integrated in 8T-SRAM cells suffers from low performance compared to double-ended complementary sensing schemes. In the proposed sensing scheme the pre-charge voltage of the single-ended read-bit-line is set to a level above the threshold voltage of the sensing device with an adjustable margin. This margin is minimized to speed up the read access on the one hand and kept large enough to provide a sufficient bit-line noise margin on the other hand. The pre-charge voltage level of the proposed sensing circuit tracks the threshold voltage of the sensing device under process variations in order to maintain a minimum required bit-line noise margin. To avoid unnecessary bit-line discharging, the proposed sensing scheme employs a modified 8T-SRAM cell. Compared to the conventional 8T-SRAM cell, the read port of the proposed cell provides a virtual ground line running in parallel to the bit-lines. An internal driver of the sensing circuit releases the virtual ground line during the evaluation period to prevent the charge dissipation resulting in a raised voltage level. The reduced pre-charge level and the increased virtual ground lead to a reduced bit-line voltage swing and thus a bit-line power reduction. Access time, energy dissipation, and noise margin of the proposed sensing circuit are compared with conventional sensing circuits from the literature for different numbers of memory cells connected to the bit-line. It is shown, that for a specific number of memory cells per bit-line the proposed circuit achieves fastest access time at low power operation.

Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications

Due to continuous scaling of CMOS, stability is a prime concerned for CMOS SRAM memory cells. As scaling will increase the packing density but at the same time it is affecting the stability which leads to write failures and read disturbs of the conventional 6T SRAM cell. To increase the stability of the cell various SRAM cell topologies has been introduced, 8T SRAM is one of them but it has its limitation like read disturbance. In this paper we have analyzed a novel PP based 9T SRAM at 45 nm technology. Cell which has 33% increased SVNM (Static Voltage Noise Margin) from 6T and also 22%.reduced leakage power. N curve analysis has been done to find the various stability factors. As compared to the 10T SRAM cell it is more area efficient.

Novel Eight-Transistor SRAM cell for write power reduction

This paper presents a novel 8T SRAM cell which contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption. The simulated results show that the proposed cell consumes about 57.87% lower power and gives faster response compared to the conventional 6T SRAM cell during a write operation. To compensate the read delay and static noise margin (SNM) losses due to the two extra tail transistors in the proposed cell, we have to enlarge the width of these two tail transistors.

Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits

This paper addresses the stability problem of diffusion-notch-free (DNF) SRAM cells used in dense last level caches (LLC). A DNF cell eliminates lithographic induced variations due to nMOS diffusion notches used in conventional 6T SRAM cells. However, it also results in reduced overall cell stability. We describe a new WL under-drive (WLUD) circuit that enables a read stable DNF cell with all minimally sized devices (called M-cell). The proposed WLUD circuit is both PT and supply noise tolerant. Write stability is maintained at low voltage thanks to a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> dynamic voltage collapse (DVC) scheme that trades large dynamic cell retention margin for improving write stability. Another DNF cell, called P-cell, with pMOS pass device and charged high bit-lines is also presented. This cell is inherently read ratio-ed and extra read margin can be obtained through upsizing the nMOS PD without creating a notch as in conventional cell. A V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> DVC circuit is used along the P-cell to recover write stability. Two SRAM macros in 45 nm were fabricated to experiment with the proposed schemes. Both simulation and measurement results confirm that ~20% WLUD along with proper V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> DVC enables a stable M-cell across a wide voltage range. A low voltage operating window for the P-cell also exists by appropriately selecting pMOS strength, nMOS pull-down size, and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> DVC.