Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits

Abstract

This paper addresses the stability problem of diffusion-notch-free (DNF) SRAM cells used in dense last level caches (LLC). A DNF cell eliminates lithographic induced variations due to nMOS diffusion notches used in conventional 6T SRAM cells. However, it also results in reduced overall cell stability. We describe a new WL under-drive (WLUD) circuit that enables a read stable DNF cell with all minimally sized devices (called M-cell). The proposed WLUD circuit is both PT and supply noise tolerant. Write stability is maintained at low voltage thanks to a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> dynamic voltage collapse (DVC) scheme that trades large dynamic cell retention margin for improving write stability. Another DNF cell, called P-cell, with pMOS pass device and charged high bit-lines is also presented. This cell is inherently read ratio-ed and extra read margin can be obtained through upsizing the nMOS PD without creating a notch as in conventional cell. A V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> DVC circuit is used along the P-cell to recover write stability. Two SRAM macros in 45 nm were fabricated to experiment with the proposed schemes. Both simulation and measurement results confirm that ~20% WLUD along with proper V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> DVC enables a stable M-cell across a wide voltage range. A low voltage operating window for the P-cell also exists by appropriately selecting pMOS strength, nMOS pull-down size, and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SS</sub> DVC.