Conventional 6T Static Random Access Memory Research Articles

A robust, low power and high speed radiation hardened 12T SRAM cell for space applications

High-energy particles found in space environment can cause single event upsets (SEUs). The severe environments found in space are too harsh for conventional 6T static random-access memory (SRAM) cell as its data get altered when a radiation particle strikes a susceptible place of the cell. Therefore, creating an SRAM that can withstand these demanding space circumstances is essential. This paper proposes a High Speed Radiation Hardened 12T (HSRH12T) SRAM cell which is suitable for low power applications and mitigates the effect of both SEU and multi-bit soft errors. All of the HSRH12T sensitive nodes are capable of recovering their data, even in the event that a radiation impact flips the node values. The HSRH12T demonstrates up to 1.6×/7.88×/1.31×/23.37× reduction in read delay (TRA), write delay (TWA), leakage and dynamic power consumption, respectively. The proposed cell exhibits up to 1.64× greater critical charge compared to the other considered cells.

Comprehensive Study of Low-Power SRAM Design Topologies

: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

Radiation tolerant capacitor-SRAM without area overhead

In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

Circuit-level design of radiation tolerant memory cell

As transistors shrink in size, the integration density of memory circuits like Static Random Access Memory (SRAM) cells rises, making them increasingly susceptible to Single Event Effects (SEE). In the space environment, memory circuits face stability and reliability challenges due to the presence of various charged particles such as α-particles, neutrons, electrons, heavy ions, and photons. These high-energy particles create ion tracks when they strike the memory device, leading to upsets in the storage bits. Conventional 6 T SRAM cells are susceptible to these upsets. As a solution this paper proposes a new Radiation Tolerable (RT 13 T) SRAM cell that is better suited for deep-space applications compared to other memory cell. RT13T has been validated to withstand radiation hazards through Critical Charge (QCrit) analysis, which shows that it exhibits 1.17×, 1.1×, 1.94× and 1.06× highest QCritthan QUCCE 10 T/12 T,traditional 6 T and LIOR 13 T memory cells, respectively. As the comparison made, our Proposed RT 13 T saved by5.1 %,9.9 %, 20.1 % and 7 % of the power consumption compared to QUCCE10T/12 T/LIOR 13 T/SERSC-16 T SRAM cells at a nominal supply voltage of 0.7 V. It also exhibits shorter read delay (TRA) 10.6 %, 1.34 %, 9.6 %, 22.16 %compared to QUCCE 10 T/12 T,6T, SERSC-16Tmemory cells, respectively. In terms of stability,our proposed RT13T SRAM cell exhibits 2.32×/2.05×/2.9×/1.05×/1.01 × higher read stability as compared with QUCCE10T/12 T/6T/LIOR 13 T/SERSC-16 T memory cells during the read operation. The our proposed RT13T shows improvements in design metrics are at the expense of a longer write delay. To characterize the performances of the proposed RT13T, 16-nm CMOS predictive technology model and validated through extensive simulation with licensed PrimeSim HSPICE of Synopsys. The results of our proposed RT13T cell are compared with some other previously proposed memory cells such as 6 T, QUCCE 10 T, QUCCE 12 T, LIOR 13 T and SERSC-16 T memory cells. The obtained results are tabulated and plotted for graphical analysis. In terms of area consumption our proposed 13 T consumes 0.9×/0.6 × lesser area than QUCCE 12 T/SERSC-16 T memory cells but our proposed circuit consumes 3.1×/1.08×/1.05 × more area than QUCCE10T/conventional 6 T/LIOR 13 T because QUCCE10T and 6 T consist of less number of transistors in memory cells.The cell proposed in this paper demonstrates strong radiation-hardened capabilities and excellent overall performance, making it well-suited for aerospace electronic devices and ensuring stable operation in space radiation environments.

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula> , respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

A 7T SECURITY ORIENTED SRAM BITCELL USING VLSI

Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of the system. Embedded memories, often implemented with six-transistor (6T) static random access memory (SRAM) cells, serve as a key component in many of these systems. However, conventional SRAM cells are prone to side-channel power analysis attacks due to the correlation between their current characteristics and written data. To provide resiliency to these types of attacks, we propose a security-oriented 7T SRAM cell, which incorporates an additional transistor to the original 6T SRAM implementation and a two-phase write operation, which significantly reduces the correlation between the stored data and the power consumption during write operations. The proposed 7T SRAM cell was implemented in a 28 nm technology and demonstrates over 1000× lower write energy standard deviation between write ‘1’ and ‘0’ operations compared to a conventional 6T SRAM. In addition, the proposed cell has a 39%–53% write energy reduction and a 19%–38% reduced write delay compared to other power analysis resistant SRAM cells. Key Words: Power Analysis, SRAM Design, 6T SRAM, 7T SRAM, Power Dissipation Software Tools:  Tanner eda Tool

Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology

A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.

A Low-Power and High-Stability 8T SRAM Cell with Diode-Connected Transistors

This research paper proposes a low-power, high-stability 8T static random access memory (SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM cell. The introduction of two diode-connected transistors in the pull-down network of the conventional 6T SRAM cell gives the proposed 8T SRAM cell structure. The presence of diode-connected transistors improves the power and noise performances of the proposed cell as compared to those of the conventional bit cells. The power consumption and static noise margin (SNM) of the suggested SRAM cell are calculated for write, hold and read operations. Also, the write and read delays of the proposed and conventional bit cells are observed. The power, speed, noise margin and area of the proposed 8T SRAM cell are compared with those of some of the existing SRAM cells. In comparison to conventional SRAM cells, the proposed cell consumes less power and has higher stability, according to the study. A novel dual-supply ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V or 200[Formula: see text]mV) concept is applied for the existing and proposed SRAM cells. The noise and power performances of SRAM cells are well improved under the condition of dual supply as compared to the conventional supply voltage ([Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V). A [Formula: see text] memory array of the proposed 8T SRAM cell is formed and the performance of the array structure is compared with that of [Formula: see text] array of the conventional 6T SRAM cell. The layouts of existing and proposed SRAM cells are illustrated. The simulation is carried out using the Cadence Virtuoso simulation EDA tool in 90-nm CMOS technology.

Half‐selection disturbance free 8T low leakage SRAM cell

SummaryThis work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses the challenge of half select by using different control signals. The cell achieves low leakage because of virtual ground (VGND), series connected tail transistor, and access series stack transistors. To study the usefulness of the proposed SRAM, it is compared with 6T, 10T, 9T, PG9T, 7T, and 8T SRAM cells. The proposed SRAM minimizes leakage power, write power, and read power by 12.4%, 21.62%, and 29.06%. Furthermore, the proposed cell improves read and write noise margin by 57.19% and 19.96%, respectively, as compared to a conventional 6T SRAM. Again, the write energy consumption lowers to about 43.86× while read energy consumption 28.95× as compared to 10T SRAM.

Monolithic and single-functional-unit level integration of electronic and photonic elements: FET-LET hybrid 6T SRAM

A broad range of technologies have been developed for the chip and wafer scale connections and integrations of photonic and electronic circuits, although major challenges remain for achieving the single-functional-unit-level integration of electronic and photonic devices. Here we use field-effect transistor/light-effect transistor (FET–LET) hybrid 6T static random-access memory (SRAM) as an example to illustrate a novel approach that can alleviate three major challenges to the higher-level integration of the photonic and electronic elements: size mismatch, energy data rate, and cascadability. A hybrid 6T SRAM with two access FETs being replaced by LETs and the electrical word lines replaced by optical waveguides is proposed. This hybrid 6T SRAM is analyzed to reveal its potential in improvement of the switching speed and thus total energy consumption over the conventional 6T SRAM. Numerical analyses, for instance, for a prototype 64 kB hybrid SRAM array, show a factor of 4 and 22 reduction in read delay and read energy consumption, and 3 and 4 in write delay and write energy consumption, respectively, when the access FETs are replaced by LETs. The potential impacts on the peripheral and assist circuits due to this hybrid structure and application of the LETs there are also briefly discussed.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current IREAD variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.

A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application

In this article, a highly reliable radiation-hardened-by-design (RHBD) 10T static random access memory (SRAM) cell is proposed. In space, the impact of alpha particles and cosmic radiation flips the node data resulting in loss of data in conventional 6T SRAM. The proposed SRAM has quad-nodes, which stores the data. The architecture is designed with a quad-latch topology and simulated in 65-nm CMOS technology with a supply voltage of 1.2 V. The result shows that the design can tolerate both 0 to 1 and 1 to 0 single event upset errors on any one of its nodes. The read and write access times of the proposed design are 88.78 and 241.77 ps, respectively. The static noise margin for read, write, and hold operations are 379.01, 906.51, and 637.1 mV, respectively. The proposed architecture takes an area of $6.52\,\,\mu \text{m}$ .

A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era

The growing demand of Internet of things based portable gadgets motivate to develop low power static random access memory (SRAM) cell. It occupies large portion in modern system on chip devices. In this context, a detailed review on various SRAM cell topologies has been performed which includes comparative analysis of design parameters and challenges. To perform the comparative analysis, considered SRAM cell topologies are simulated with cadence virtuoso IC6.1.5-64b at 45 nm generic process design kit technology file. It is worthy to notice that 9T SRAM cell has highest value of read stability among considered cells. It is attributed to use of differential read decoupled structure. The 7T SRAM cell has highest value of write ability among considered cells. It is observed that 8T SRAM cell has lowest read power dissipation among considered cells. It happens due to the use of stack transistor in read path of the cell. The lowest value of read access time is also observed in 8T SRAM cell among considered SRAM cells. It is 1.82 $$\times$$ higher as compared to conventional 6T SRAM cell. Further, the write access time of 9T SRAM cell is lowest among considered cells. This is 1.41 $$\times$$ less as compared to conventional 6T SRAM cell. Static noise per unit area to power delay product ratio (SAPR) is used to evaluate the overall performance of considered SRAM topologies. It is observed that 8T SRAM cell has the highest value of SAPR among considered SRAM cells. It is 1.91 $$\times$$ as compared to conventional 6T SRAM cell. All the comparison has been done at 1.0 V supply voltage.

Design of multi-cell upset immune single-end SRAM for low power applications

The on-chip static random access memory (SRAM) has been under revamp due to swift growth in demand of power-efficient internet-of-things based devices. In this context, a low power transmission gate based read decoupled 9-transistor (TRD9T) SRAM bit-cell has been proposed in this work. The proposed cell efficiently minimizes the power dissipation in terms of static/dynamic power and maintains the stability during read, write and standby mode as compared to five recent reported designs. The proposed cell is less vulnerable to soft errors due to improved critical charge that is followed elimination of half-select issue that facilitates bit-interleaved implementation. In addition to conventional 6T (Conv.6T) SRAM, it has been compared with five already reported designs such as tunable-access 8T (TU8T), single ended disturb free 9T (SEDF9T), P-P-N based 10T (P10T), low power 10T (LP10T) and data dependent 11T (D11T) bit-cells, for evaluating the relative performance of proposed design in terms of key design metrics. The reduction in soft error in proposed design is indicated by 1.14×/1.07×/0.99×/1.39×/1.05× improvement in critical charge in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T respectively. The proposed cell mitigates half-select issue to achieve the capability of implementing bit-interleaved architecture. Moreover, standby power of proposed design is reduced by 2.01×/2.46×/1.58×/0.79×/1.89×/1.90× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively and this improvement sustains at temperature variation from at 27 °C to 110 °C. The TRD9T exhibits 1.97×/1.87×/1.01×/1×/1.01×/1.78× higher read static noise margin and 1.17×/1.21×/1.44×/1.44×/1.11×/0.85× higher write static noise margin in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively. Also, 1.70×/1.29×/2.09×/1.49×/1×/1.60× and 1.48×/1.77×/2.75×/1.77×/1.64×/2.28× improvement in read power and write power respectively is achieved in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. The read access time of proposed design is improved by 1.31×/1.01×/2.12×/1.18×/1.01×/1.13× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. Proposed TRD9T show narrower variability in read stability, read power and read current in comparison to conv. 6T. The proposed TRD9T also exhibits best Electrical quality metric (EQM) among the cells considered in this work.

A Schmitt-trigger based low read power 12T SRAM cell

In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52 $$\times$$ and 1.86 $$\times$$ lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by $$1.71 \times /1.82 \times$$ as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation.

A low-power small-area 6T SRAM cell for tracking detector applications

This paper presents a novel six-transistor (6T) Static Random Access Memory (SRAM) cell, which uses only one bit line and applies an additional switch to cut the competition path during the write access. The proposed 6T SRAM cell has been applied in a pixel array detector to configure a digital-to-analog converter in each pixel to improve the charge threshold uniformity. Compared to the conventional 6T SRAM cell, the proposed 6T SRAM cell features lower power consumption and smaller area. Simulation results show the power consumption is reduced by about 43% and all the transistors are designed by minimum size to reduce the area but without the performance degradation. The test results show that the novel 6T SRAM cell works very well.