Continuous-wave Laser Lateral Crystallization Research Articles

Performance evaluation of polycrystalline Si1−xGex thin-film transistors fabricated by continuous-wave laser lateral crystallization on glass substrates

This study was aimed at elucidating the performance of continuous-wave laser lateral-crystallized (CLC) polycrystalline Si1−xGex (poly-Si1−xGex) thin-film transistors (TFTs). The transfer characteristics of the n-ch CLC poly-Si1−xGex TFTs (x = 0, 0.05, 0.1, and 0.3) exhibited a positive shift in the threshold voltage (Vth) with increasing Ge content. Furthermore, the off-current in the p-ch CLC poly-Si0.9Ge0.1 TFTs decreased with decreasing film thickness. These properties of the CLC poly-Si1−xGex TFTs can be attributed to the generation of acceptors and increment of gate SiO2/poly-Si1−xGex interface charge state with increasing Ge content. The generation of acceptors was also supported by Hall effect measurements. In addition, the thermal stability of acceptors up to 700 °C was elucidated through Hall effect measurements and TFT performance evaluations. Furthermore, we examined the origins of these acceptors. This experiment highlighted the sensitivity of Si1−xGex to Ge incorporation, even in small amounts.

Isotropic TFT Characteristics in the {100}-Oriented Grain-Boundary-Free Laser-Crystallized Si Thin Films

Isotropic TFT characteristics are realized in the {100}-oriented grain-boundary-free 60 nm thick Si film obtained by the continuous-wave laser lateral crystallization, where the grain- and sub-boundaries are defined as the crystallographic boundaries having misfit angles of θ > 15° and θ < 15°, respectively. Sub-boundaries are observed in the film parallel to the scan directions; the misfit angles were 5–10° and the sub-boundary density was 0.02956 μm−1. Sub-grains, joined by the sub-boundaries, have widths of 8 ~ 69 μm. The cumulative distributions of mobility, threshold voltage, and subthreshold swing agree well between the parallel and perpendicular TFTs in the film, where parallel or perpendicular means the source-to-drain directions to the laser scan direction. The maximum mobilities of the parallel and perpendicular TFTs are 695 and 663 cm2/Vs, respectively. The trap-state density NT in the sub-boundaries estimated from the product of the bond efficiency η and the dangling bond density decreases by two decades from those of the grain boundaries. A new carrier transport model of the current flow across the sub-boundary is proposed instead of the thermionic emission model for the grain boundaries.

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

This study aims to understand the performance of continuous-wave laser lateral crystallization (CLC) poly-Si1-xGex TFTs. The transfer characteristics of n-ch CLC poly-Si1-xGex TFTs revealed that the threshold voltages shifted in the positive direction compared with those of CLC poly-Si TFTs with increasing Ge concentration. The characteristics of CLC n-ch poly-Si1-xGex TFTs can be explained by the formation of acceptors. For p-ch TFTs, the transfer characteristics of CLC poly-Si1-xGex TFTs exhibited a larger Ioff than those of CLC poly-Si TFTs. The Ion/Ioff ratio is small for p-ch parallel CLC poly-Si1-xGex TFTs and is weakly dependent on the gate length. In contrast, p-ch perpendicular CLC poly-Si1-xGex TFTs exhibit large Ion/Ioff values for long gate lengths. The variation in the Ion/Ioff ratio of p-ch CLC poly-Si1-xGex TFTs according to the parallel or perpendicular and long or short gate length is explained by Ge segregation along the grain boundary, resulting in the formation of a high-concentration p-type conduction region along the grain boundary, which connects the SD regions.

Continuous-Wave Laser Lateral Crystallization of A-Si Thin Films on Polyimide Using a Heatsink Layer Embedded in the Buffer SiO2

Continuous-wave laser crystallization of amorphous Si (a-Si) thin films on a polyimide (PI)-coated glass substrate is studied by using a single scan of a highly uniform top-flat line-beam with a 123 nm SiO2 cap layer and a thin buffer layer at room temperature in air. The total buffer layer thickness is reduced to as thin as 1.55 μm including the heatsink a-Si layer and two SiO2 layers. Damage to the polyimide during the crystallization is successfully suppressed by the heatsink layer. An 88.3% {100} surface fraction is obtained for a 60-nm-thick Si thin film within 15° on polyimide even with a low scan velocity of 15 mm/s.

Characterization of selectively oriented polycrystalline silicon thin films formed by multiline beam continuous-wave laser lateral crystallization with overlapping

The uniformity of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) over a large scale is an important element in their application. Characteristics of poly-Si thin films are the key factors influencing the performance of TFTs. In this area, we developed void-free (100)-surface oriented poly-Si thin films over large areas using multiline beam continuous-wave laser lateral crystallization (MLB-CLC) with overlapping scanning. Predominantly (100)-surface oriented poly-Si thin films are formed over large areas with the laser power from 5 to 8 W. (100), and random, or (211)-surface orientations can be selected by varying the laser power and scanning speed. In addition, characterization of these selectively oriented poly-Si thin films is analyzed using two-dimensional X-ray diffraction and hard X-ray photoelectron spectroscopy.

Extension of the {100}-Oriented Grain-Boundary Free Si Thin Film Grown by a Continuous-Wave Laser Lateral Crystallization

A steady-state crystal growth of a {100}-oriented grain-boundary free 60 nm-thick Si thin-film is realized so long as the laser scan continues by the continuous-wave laser lateral crystallization of amorphous-Si on quartz, resulting in a huge grain of 3000 μm long and 120-150 μm wide. At an increased power by 0.1 W from the optimum power, a stable grain growth is realized as well, but it takes a longer scan travel to get the steady-state crystal growth than that at the optimum. With a disturbance on the way of the scan at the optimum power, the steady-state crystal growth continues to the vicinity of the disturbance, and it tends to recover with further scan after the disturbance even with the nano-crystal region formed at the disturbance region.

Unseeded Crystal Growth of (100)-Oriented Grain-Boundary-Free Si Thin-Film by a Single Scan of the CW-Laser Lateral Crystallization of a-Si on Insulator

Laser crystallization of a-Si film on insulating substrate is a promising technology to fabricate three-dimensional integrations (3D ICs), flat panel displays (FPDs), or flexible electronics, because the crystallization can be performed on room temperature substrate to avoid damage to the underlying devices or supporting plane. Orientation-controlled grain-boundary-free films are required to improve the uniformity in electrical characteristics of field-effect-transistors (FETs)fabricated in those films. This paper describes the recently found simple method to obtain {100}-oriented grain-boundary-free Si thin-films stably, by using a single scan of continuous-wave (CW)-laser lateral crystallization of a-Si with a highly top-flat line beam with 532 nm wavelength at room temperature in air. It was difficult to control crystal orientations in the grain-boundary-free film crystallized by the artificial modulation of solid-liquid interface, and any other trial to obtain preferential surface orientation with multiple irradiations resulted in grain boundaries. The self-organized growth of the {100}-oriented grain-boundary-free films were realized by satisfying the following conditions: (1) highly uniform top-flat line beam, (2) SiO2 cap, (3) low laser power density in the vicinity of the lateral growth threshold, and (4) single scan crystallization. Higher scan velocity makes the process window wide for the {100}-oriented grain-boundary-free film. This crystallization is very simple, because it is performed by a single unseeded scan with a line beam at room temperature substrate in air.

Effect of surface tension on crystal growth of Si thin films by a continuous-wave laser lateral crystallization

Effect of surface tension and temperature distribution on the crystal growth of Si thin films by continuous wave laser lateral crystallization is experimentally investigated in comparison with the capped and non-capped samples. It is proposed that the grain-boundary free (100) film is realized by the averaged solid–liquid interface which holds an angle of ∼45° to the substrate. This theory explains well the effects of surface tension and laser power.

Transition mechanism of the thin Si-films obtained by the CW laser lateral crystallization from the grain-boundary free highly {100} oriented crystal to the twinned {211} crystal depending on the laser power

Surface texture transition from grain-boundary free {100} crystals to twinned {211} was observed with increasing laser power in the crystal growth of low-temperature silicon films by the cw laser lateral crystallization of a-Si. This transition is explained by two step mechanism. Firstly a crystal having ∼{110} texture grows in the scan direction (SD) rotated from {100} texture keeping the {100} surface normal texture with increasing laser power, and secondly the deformation twinning occurs in the solidified crystal having an in-plane rotation angle of 35°–45° by the compressive stress due to the Si volume expansion with further increasing power, but the twinning does not occur even with the same compressive stress in the crystal having an in-plane rotation angle of 0°–33.5°, where the rotation angle is defined as the angle between 〈100〉 axis of the grown crystal and the SD. The reason is explained by the Schmidt factor calculated as a function of the in-grain rotation with the laser power, assuming the compressive stress is applied parallel to the isotherms. The maximum value in the Schmidt factors for possible partial dislocation glides was 0.471 for the crystal having {110} texture in the SD and 0.236 for the crystal having {100} texture in the SD. Resolved stress to move the twinning partial dislocation in the crystal having {110} texture in the SD is higher than that in the crystal having {100} texture in the SD by a factor of 2.

57‐3: Folded Pixel Circuit Design in Grain‐Boundary Free (100) Oriented LTPS Stripes Fabricated by Selective CW‐laser Lateral Crystallization

Effects of scan conditions on grain‐boundary‐free (100) oriented LTPS films by the CW laser lateral crystallization were investigated. Overlapped scans generated grain‐boundaries at the scan regions. A new selective one‐time scan was proposed for high precision mobile OLED panels, where LTPS circuits of neighboring pixels were folded along the scan.

Formation of (100)-oriented large polycrystalline silicon thin films with multiline beam continuous-wave laser lateral crystallization

Low-temperature crystallization to (100)-oriented polycrystalline silicon (poly-Si) thin films is a key requirement for high-performance low-temperature poly-Si thin-film transistors (LTPS-TFTs). Biaxially (100)-oriented poly-Si thin films were formed by multiline beam continuous-wave laser lateral crystallization in single scans. By overlapping scanning, the (100) preferential orientation was stable and (100) silicon crystals were developed over a large area. The crystallinities of the poly-Si films were precisely characterized, especially by two-dimensional X-ray diffraction. It was found that the poly-Si thin films predominantly had (100)-surface-oriented crystals. The crystallinity of the laser-crystallized poly-Si films was dependent on the scanning speed and overlapping condition. The (100) poly-Si films were formed at scanning speeds below the threshold for lateral-crystallized silicon.

Performance of four-terminal low-temperature polycrystalline-silicon thin-film transistors and their application in CMOS inverters on glass substrates

High-performance and low-power-operation CMOS circuits comprising low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for integrated circuits on glass substrate. The fabrication of high-quality poly-Si films with large grains can enhance the on-current of TFTs on glass substrates owing to low carrier scattering. In this study, we used continuous-wave laser lateral crystallization (CLC) to fabricate high-quality thin poly-Si films on a glass substrate. To achieve low-power operation, precise threshold voltage (Vth) control is most important, and four-terminal (4T) TFT is one attractive approach to achieve it. We fabricated a CMOS inverter comprising 4T CLC LT poly-Si TFTs on a glass substrate and confirmed nearly identical controllability of Vth, subthreshold swing, and mobility of n- and p-channel TFTs in CMOS inverter as compared with TFTs fabricated on different glass substrates with their own processes. By using the high controllability of 4T CLC LT poly-Si TFTs, we successfully operated the CMOS inverter with Vdd = 1.0 V.

Power dependence of orientation in low-temperature poly-Si lateral grains crystallized by a continuous-wave laser scan

A low-temperature poly-Si film with 99.8% {100} texture in the surface normal direction within 10° is obtained by single-scan continuous-wave laser lateral crystallization of 60nm-thick a-Si without a seed at room temperature in air. This texture extends over the entire melted width of 105μm except for narrow edge regions and is maintained for the full scan length of 1.8mm. Highly {100}-oriented films in the surface-normal direction are obtained at the low net laser power P(1-R) of 1–1.25W above the threshold for the lateral grain growth, where P is the incident total power, and R is the reflectivity of the sample. A second power threshold exists where the degree of the {100} surface-normal texture begins to decrease above the first threshold for lateral grains. Above the second threshold, the percentage of the {100} surface-normal texture decreases linearly with the increasing P(1-R) at the same slope of 20% in 0.1W change for all the samples with different cap thicknesses.

Ultrahigh-performance (100)-oriented polycrystalline silicon thin-film transistors and their microscopic crystal structures

A multiline beam continuous-wave laser lateral crystallization (MLB-CLC) method was developed to realize a predominantly (100)-oriented polycrystalline silicon (poly-Si) film with a high biaxial tensile strain. Low-temperature poly-Si (LTPS) thin film transistors (TFTs) with an ultrahigh maximum electron field effect mobility of 1010 cm2 V−1 s−1 were realized. The correlation between the performance and microscopic crystallinity of the TFTs was investigated. The performance enhancement of TFTs brings about highly (100)-surface-oriented large Si crystallites with a high biaxial tensile strain and grain boundaries being parallel to the current flow.

(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization

Low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for applications that involve integrating high-speed and low-power dissipation complementary metal-oxide-semiconductor (CMOS) circuits onto a glass substrate. The on-current of the LT poly-Si TFTs can be enhanced by fabricating a high-quality poly-Si film on the glass substrate. In the current study, the fabrication of these transistors was achieved using continuous-wave laser lateral crystallization (CLC). This method enabled us to form a lateral poly-Si film with high quality and large grain size (the grain area was approximately 100 times larger than that of the conventional excimer-laser crystallization (ELC) poly-Si film) without damaging the substrate. A possible approach to achieve low-power dissipation is by controlling the threshold voltage (Vth). In order to control the Vth of the LT poly-Si TFTs, we fabricated self-aligned four-terminal (4T) LT poly-Si TFTs using high-quality CLC poly-Si film. These TFTs comprise metal gates on the top and bottom. The bottom metal gate was embedded in the glass substrate using a chemical mechanical polish. The top metal gate was fabricated by a self-aligned process of back surface exposure using the bottom metal gate as a photomask. This TFT was fabricated on a fused quartz glass at 550°C. The top and bottom metal gates acted as drive and control gates, respectively, or vice versa. The performance of the fabricated n-channel (n-ch) and p-channel (p-ch) self-aligned 4T CLC LT poly-Si TFTs was evaluated. To evaluate their feasibility, an E/D inverter was utilized by connecting two identical n-ch TFTs on different glass substrates, which were fabricated by identical processes.The self-aligned 4T CLC LT poly-Si TFTs showed excellent Vth controllability. The variation of the Vth of the drive gate TFT, with respect to small variation in the control gate voltage, was found to closely match the theoretically predicted values of the top and bottom gate drives for both n- and p-ch TFTs. The output characteristics of the drive TFTs were found to be sensitive to the varying magnitude of the control gate voltage. The mobility of the n-ch TFTs in the top and bottom drive TFTs was above 300 cm2/Vs. This remarkable performance may be attributed to the high-quality CLC poly-Si film. The mobility varied sensitively against the strength of the vertical electric field, which was changed by varying the control gate voltage. The s.s. values were also found to vary depending on the control gate voltage, and this variation is explained by the change in the position of the channel layer towards the side of either the drive or the control gate. By exploiting the high controllability of the 4T TFTs, an E/D inverter was fabricated and successfully operated at 2.0 V. The Vth of the self-aligned 4T CLC LT poly-Si TFTs was found to be sensitive to a 20-meV variation of the control gate voltage. Utilizing this sensitivity, we further fabricated an extended-gate pH sensor, where the control gate was connected to the glass electrodes, and the pH of the solution varied from 4.1 to 8.8. Consequently, we were able to successfully observe the variation of the drain current in the drive gate TFT depending on the strength of pH. In summary, the results suggest that the high controllability of the self-aligned 4T CLC LT poly-Si TFTs could enable us to fabricate high-speed and low-power-dissipation circuits on a glass substrate. Further, our study suggests the promising potential of such TFTs for applications involving sensor fabrication.

Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved. Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced. Figure 1

Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization

(100)-dominantly oriented poly-Si film was realized by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping. Si grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. In this work, the device characteristics of the fabricated TFTs are investigated. Fabrication process of the poly-Si TFTs are as follows: A buffer SiO2 layer of 1 μm thickness was deposited on a quartz substrate by Plasma-Enhanced Chemical Vapor Deposition (PECVD). Sequentially, an amorphous Si (a-Si) film of 150 nm thickness and a cap SiO2 of 100 nm thickness were deposited by PECVD. The films were dehydrogenated by furnace annealing at 490 oC in N2 ambient for an hour before crystallization with MLB-CLC (wavelength: 532 nm, laser power: 6 W). The laser beams scanned the sample at a speed of 0.8 cm/s with an overlapping ratio of 83%. After the cap SiO2 layer was etched by buffered hydrofluoric acid (BHF) solution, the poly-Si active layer was patterned using lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm). Gate oxide SiO2 of 42 nm thickness was deposited by Electron cyclotron Resonance (ECR) Plasma Chemical Vapor Deposition (SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and Mo gate electrode of 300 nm thickness was deposited by sputtering. Patterning gate electrodes was carried out by lithography and wet etching (H3PO4:HNO3:CH3COOH:H2O = 400:25:50:25), followed by self-aligned source and drain formation by As ion implantation (ion dose: 2 x 1015 cm-2, accelerating voltage: 66 kV) using the Mo gate as mask. Activation annealing treatment was performed at 550 oC in N2 ambient for 30 minutes. Before SiO2 insulator film of 600 nm was deposited by Atmospheric Pressure Chemical Vapor Deposition (APCVD), sacrificial SiO2 in source and drain region was etched by BHF. Contact hole was formed by lithography and BHF wet etching. Mo metal pad of 700 nm thickness was deposited by sputtering and patterned by lithography and wet etching. Finally, the sample was annealed at 400 oC in H2 ambient for 30 minutes. The highest temperature of the fabrication processes was 550 oC. The devices were designed with the width and length of channel of W = 10 µm and L = 10 µm, respectively. Figure 1 shows microphotograph of poly Si film and schematic of TFT designed mask. This result reveals that poly-Si film was periodic in 200 µm and the channels were fabricated parallel with scanning direction in 10 groups at different positions. In particular, TFTs of group 1 were fabricated along heavy-void regions and distance of two consecutive groups was 20 µm in perpendicular direction of laser scan. Figure 2 shows an EBSD mapping of the laser-crystallized poly-Si films. It was found that (100) Si crystal grains with an average size of 20 µm x 2 µm were formed. In this figure, crystal orientation of the poly-Si film was different from the middle to the side of the measured region. As result, characteristics of TFTs was relatively different in each group. Table I indicates average mobility, maximum mobility, and variation of TFTs in 10 groups. TFTs with ultrahigh electron field effect mobility (µFE ) of over 1000 cm2/Vs in a linear region was realized. A high average electron field effect mobility of 636 cm2/Vs and its low variation of 25% were achieved in group 7 in which (100) Si crystal grains were dominant. Figure 3 shows IDS-VGS characteristics of poly Si TFTs in group 7. A high off-leakage current and its high variation of 10-10 – 10-6 were observed owing to trap states in both the grain boundaries and crystal grains. Table I.Average mobility of TFTs and their variation in each group Group Average mobility (cm2/Vs) Maximum mobility (cm2/Vs) Standard deviation (cm2/Vs) 1 2 3 4 5 6 7 8 9 10 270 490 453 476 510 590 636 600 632 618 512 1010 780 717 697 873 971 940 973 808 114 264 131 148 79 167 159 194 183 118 Figure 1

Extended-Gate pH Sensors Using Self-Aligned Four-Terminal Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate

High-performance polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) on glass substrate are applicable to high-performance and low-cost pH sensors. We previously reported on four-terminal (4T) self-aligned planar embedded metal double-gate (E-MeDG) low-temperature (LT) poly-Si TFTs on glass substrate. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are fabricated from a sputtered tungsten film. The BG is embedded in the glass substrate through chemical mechanical polishing, and the TG is fabricated in a self-aligned manner to the BG by using back-surface exposure. The material of the gate dielectric is silicon dioxide (SiO2), which is deposited using plasma-enhanced chemical vapor deposition, and has a thickness of 75 and 150 nm against the TG and BG, respectively. The material of the channel region is poly-Si, which is fabricated using diode-pumped solid-state continuous-wave laser lateral crystallization. The TG and BG can be used as the drive and control gates, and vice versa. In this device, we were able to control the threshold voltage (Vth) by varying the voltage applied to the control gate, and we confirmed a high Vth controllability. This Vth controllability is applicable for pH sensors because voltage variation applied to the control gate due to a change in pH can be read as the Vthvariation of the TFTs. Therefore, the 4T self-aligned planar E-MeDG LT poly-Si TFT can be used as an extended-gate field-effect transistor (EGFET) to measure the voltage variation due to a change in pH. Thus, we performed an evaluation of pH sensors by using the 4T self-aligned planar E-MeDG LT poly-Si TFT as an EGFET. The evaluation of pH sensors was performed using a typical glass electrode, reference electrode, and pH buffer solution in addition to the 4T self-aligned planar E-MeDG LT poly-Si TFTs. The glass electrode was connected to the TG or BG of the TFTs. The reference electrode was connected to the electrode, which applied a constant voltage. The glass electrode and reference electrode were set in the pH buffer solution. In this situation, we evaluated the pH sensors by measuring the transfer characteristics of the TFTs by using another gate, which was not connected to the glass electrode, as the drive gate. In the first experiment, we connected the glass electrode to the BG and measured the transfer characteristics by using the TG as the drive gate against pH = 8.8 and pH = 4.2 buffer solutions under various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.8 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.2 buffer solution at every reference electrode voltage. The pH sensitivity calculated from the Vthvariation is 21.7 mV/pH, which is fairly consistent with the theoretical pH sensitivity of 25.5 mV/pH. In the second experiment, we connected the glass electrode to the TG and measured the transfer characteristics by using the BG as the drive gate against pH = 8.7 and pH = 4.8 buffer solutions at various reference electrode voltages. We confirmed that the transfer characteristics of the drive gate in the pH = 8.7 buffer solution shifted toward the positive direction against the characteristics in the pH = 4.8 buffer solution. This trend is the same as that of the top-gate drive TFT, but the pH sensitivity calculated from the Vthvariation is 76.9 mV/pH, which is larger than that of the top-gate drive TFT. In addition, its magnitude is found to be fairly consistent with the theoretical pH sensitivity of 88.8 mV/pH. We consider that the difference in pH sensitivity between the TG and BG drives is caused by the difference in thickness between the TG and BG SiO2 dielectric. We previously confirmed that the ratio of the Vthvariation against the control gate voltage variation is larger in the BG drive than in the TG drive. We consider that the difference in pH sensitivity reflects this phenomenon. Thus, the experimental results indicate that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In summary, we confirmed that 4T self-aligned planar E-MeDG LT poly-Si TFTs can be successfully operated as pH sensors. In addition, to improve the pH sensitivity of EGFETs, our experimental results indicate that the combination of the capacitance of the top and bottom gates is a significant parameter.

(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization

To integrate circuits on a glass substrate, high-performance and low-power-dissipation low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable. Fabrication of high-quality poly-Si film is one approach to enhance the on-current of LT poly-Si TFTs on a glass substrate. In this paper, we used continuous-wave laser lateral crystallization (CLC) to fabricate high-quality lateral large-grained poly-Si films on a glass substrate. To achieve low power dissipation, threshold voltage (Vth) control technology is one tentative approach. To control the Vth of LT poly-Si TFTs, we fabricated four-terminal (4T) self-aligned embedded metal double-gate (E-MeDG) LT poly-Si TFTs using high-quality CLC poly-Si films. The 4T self-aligned E-MeDG CLC LT poly-Si TFTs showed excellent Vth controllability. By exploiting the high controllability of the 4T TFTs, E/D inverter and extended gate pH sensor were fabricated and successful operation with high performance was confirmed.