Continuous-time Delta-sigma Modulator Research Articles

A 4.5 nV/√Hz Capacitively Coupled Continuous-Time Sigma-Delta Modulator with an Energy-Efficient Chopping Scheme

When chopping is applied to a continuous-time sigma-delta modulator (CT ${\Sigma \Delta }\text{M}$ ), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator’s feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CT ${\Sigma \Delta }\text{M}$ intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator’s summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/ ${\surd }$ Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.

A Fully Integrated Current-Mode Continuous-Time Delta-Sigma Modulator for Biological Nanopore Read Out.

This paper presents a fully integrated low noise current-to-digital converter based on current-mode continuous-time delta-sigma modulators (CT DSMs). The circuit was realized in standard 0.35 μm complimentary metal-oxide-semiconductor process and achieves a noise floor as low as 200fA rms within a bandwidth of 10kHz. Thanks to the continuous-time architecture, the oversampling together with the implicit anti-aliasing behavior of the current-mode CT DSM prevents the back folding of any out-of-band signals and noises. Running at a sampling frequency of 1.6MHz, the circuit achieves a measured worst case anti-aliasing filtering of -110dB for an out-of-band signal at 1.59MHz. This characteristic eliminates the need of an anti-aliasing filter, which reduces the complexity as well as the area and power consumption. Two feedback versions, a transistor based as well as a capacitor-based current division have been used to reduce the reference current noise. The transistor-based current division feedback modulator consumes a power of 6.73mW and occupies an area of 0.63mm 2, whereas the capacitor based consumes a power of 4.6mW and occupies an area of 0.32mm 2. Both of them operate at a supply voltage of ±1.5V.

A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer

This paper presents a continuous-time delta-sigma modulator using a double noise-shaped quantizer (DNSQ), which not only provides 2nd-order noise shaping but also generates a 6-bit quantization in the modulator. The proposed DNSQ efficiently extracts the quantization error in the time domain from a noise-shaped integrating quantizer (NSIQ), and directly applies it to a gated ring oscillator-based quantizer, hence achieving a 2nd order of noise shaping on its own. By incorporating the DNSQ, the modulator can achieve 4th-order noise shaping with only a 2nd-order loop filter. The proposed modulator is fabricated in a 0.13- $\mu \text{m}$ CMOS process with an active area of 0.17 mm2. It operates at 640 MHz and achieves a peak SNDR of 80.4 dB in a 15-MHz bandwidth while consuming 11.4 mW from a 1.2-V power supply.

A Power-Efficient Readout for Wheatstone-Bridge Sensors With COTS Components

This paper presents a direct digital converter for Wheatstone bridge sensors, which is realized with commercial off-the-shelf components. The power efficiency of the readout is enhanced by embedding the bridge sensor in a second-order continuous-time sigma-delta modulator ( ${\mathrm{ CT}}\Delta \Sigma {\mathrm{ M}}$ ). By directly digitizing the output signal of a Wheatstone bridge in the current mode, the noise performance is dominated by the operational amplifier in the first integrator and the bridge sensor. To demonstrate the performance of the proposed circuit, an MEMS piezoresistive differential pressure sensor is used. Measurement results show that a resolution of 12.7 mPa $_{\mathrm {{rms}}}$ (0.41 $\text{m}\Omega _{\mathrm {{rms}}}$ ), with a 0.5-ms conversion time, can be achieved. Powered by 5 V, the circuit and the bridge sensor draw 9.55 and 7.58 mW, respectively.

Analysis of effect of feedback current variation in CT Delta-Sigma modulators with Gm-C integrators

In design of Continuous-time Delta-Sigma modulators, the feedback DAC (Digital-to-Analog Converter) is typically implemented with a switched current circuit. It is desired that these DAC current circuits provide constant current across clock cycles for each modulator output level. However, when Delta-Sigma modulators are implemented with Gm-C integrators, the DAC feedback current circuits are directly connected to the integrator outputs that may have high-swing voltages and this results in varying DAC feedback current. In this paper, we analyze the effect of feedback current variation caused by high-swing integrator output voltages in Delta-Sigma modulators built with Gm-C integrators. It is shown that feedback current variation may significantly degrade the performance of Delta-Sigma modulators mainly due to the non-linearity of current variation dependence on the integrator output voltage, while mismatch of current variation has minor effect.

Passive Loop Filter Assistance for CTSDMs

This brief presents a power reduction technique for continuous time sigma–delta modulators (CTSDMs). The approach consists of two elements. First, a passive low-pass filter is added in front of the modulator’s loop filter to reduce the high frequency components in the loop. As a result, the slew rate requirements of the opamps can be greatly reduced which allows a significant power saving. Unfortunately, the insertion of this low-pass filter also changes the modulator’s loop gain, and hence affects the noise transfer functions (NTFs) and signal transfer functions (STFs), in an undesired way. Therefore, the second proposed element consists of inserting a compensation branch which is such that the original loop gain, NTF and STF are restored. Thanks to this, our power saving technique is completely transparent on the system level such that all established techniques and toolboxes for CTSDM design can still be used. The technique is especially suited for one-bit CTSDMs, where the amount of high-frequency components in the loop is excessive. To showcase the technique, a self-oscillating sigma–delta modulator (which is a dedicated type of one-bit CTSDM) was implemented in a 65-nm CMOS process. It achieves a peak signal to noise and distortion ratio of 63 dB over a 20-MHz bandwidth at a power consumption of 1.7 mW while occupying a very small chip area of only 0.009 mm2.

A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS

An area-efficient voltage-sensing readout circuit employing chopped voltage-controlled oscillator (VCO)-based continuous-time delta-sigma modulator (CTDSM) is presented in this paper. This VCO-based CTDSM features direct connection to sensors to eliminate pre-amplifier for achieving better hardware efficiency. The VCO is designed as a trans-conductor current-controlled oscillator, which is a fully differential $G_{m}$ stage cascaded with two CCOs, to provide a high-input impedance to sense the voltage signals from sensors. Analysis shows that the main noise and offset contributor is the $G_{m}$ stage. This problem is mitigated by employing choppers at critical location within the circuit. The VCO-based CTDSM is implemented in a 40-nm CMOS process. The power consumption is $17~\mu \text{W}$ under 1.2-V supply. With a 4-mVp (8-mV $_{\textrm {pp}})$ input, it achieves 61.85-dB signal-to-noise-and-distortion ratio over a 5-kHz bandwidth and the total harmonic distortion is −70.8 dB. The input-referred noise is 32 nV/ $\surd $ Hz. The chip area is only 0.0145 mm $^{\textrm {2}}$ .

Quad Mode of Sixteen Channel Chopper AFE Design and Cascaded with Continuous Time Sigma Delta Modulator for Electroencephalogy Monitory System

Quad Mode of Sixteen Channel Chopper AFE Design and Cascaded with Continuous Time Sigma Delta Modulator for Electroencephalogy Monitory System

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below.

Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design

Chopping is a commonly used technique to eliminate flicker noise in amplifiers. We investigate the use of chopping in the input integrator of a continuous-time oversampling ( $\Delta \!\Sigma $ ) converter. Unlike an amplifier, the integrator in a continuous-time delta-sigma modulator is subject to out-of-band signals that are several orders of magnitude higher than the (desired) in-band component. This necessitates a careful analysis of frequency translation effects in a chopped integrator. This paper treats the chopped integrator as a linear periodically time-varying system, and exploits the adjoint (inter-reciprocal) network concept to simplify the analysis of aliasing effects in such an integrator. Simulation results that confirm the theory are given.

A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping

This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog-to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma–delta modulator (CT-SDM). The counter consists only of digital building blocks, and the VCOs are implemented using ring oscillators, which are also digital-friendly. No traditional analog blocks, such as opamps, OTAs, or comparators, are used. As a proof of concept, we have implemented a third-order VCO-based CT-SDM for a 10-MHz bandwidth in the low-power version of a 65-nm CMOS technology. This prototype shows a measured performance of 71/66.2/62.5-dB DR/SNR/SNDR at a 10-MHz bandwidth while consuming 1.8 mW from a 1.0-V analog and 1.9 mW from a 1.2-V digital supply. With digital calibration, the nonlinearity could be pushed below the noise level, leading to an improved peak SNDR of 66 dB.

Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator

Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator

Time‐shifted excess loop delay compensation DAC for 2‐ T s delay in CT‐ΔΣ ADCs

This Letter proposes a new two-sample excess loop delay compensation in continuous-time delta-sigma modulators using time-shifted differentiated digital-to-analogue converter (DAC). This is done by using the information inherently available but ignored in the conventional methods, and therefore no additional hardware is required. Simulation results and mathematical analysis are provided to verify the effectiveness of the proposed structure.

A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer

A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage swing operation, in which the excess-loop-delay compensation is embedded without requiring additional hardware. With a 240-MHz sampling clock, this CTDSM achieves a peak SNDR of 68.3 dB and a dynamic range of 71 dB over a 5-MHz signal bandwidth. Fabricated in a 90-nm CMOS process, this chip consumes 4.6 mW from a 1-V supply, which corresponds to a figure of merit (FoM) of 216 fJ/conversion-step.

A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

A 4-bit, third-order, continuous-time $\Sigma \Delta$ modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance $\Sigma \Delta$ modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm2.

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A fourth-order quadrature bandpass continuous-time sigma–delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital–analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.

A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage

A wide-bandwidth (BW) power-efficient continuous-time ΣΔ modulator (CTΣΔM) is presented. The modulator introduces a third-order filter implemented with a lossless integrator and a multiple-feedback single-amplifier biquadratic filter with embedded loop stability compensation. An active summing block is implemented by employing a common-gate current buffer followed by a transimpedance amplifier. This combination relaxes the specification requirements of the operational amplifier by making its required BW independent of the closed-loop gain. The proposed technique achieves optimum BW with reduced power consumption, making it functional for over gigahertz operation. Fabricated in a standard 40-nm CMOS technology, and clocked at 3.2 GHz, the CTΣΔM achieves a signal-to-noise-and-distortion ratio of 65.5 dB over 75-MHz BW while consuming 22.8 mW of power. The obtained Walden's figure of merits is 98 fJ/conv-step.

A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT $\Sigma \Delta \text{M}$ ) with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT $\Sigma \Delta \text{M}$ stages, each of which consists of an integrator-based active- RC loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip RC time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as $\text {FOM}=\text {SNDR}+10\times \log _{10}(\text {BW}/\text {P})$ , is 165.1 dB.

A low power reconfigurable multi-mode continuous time Delta Sigma modulator for seven different mobile standards with VCO-based quantizer

In this research a novel low power multi-mode continuous time Delta Sigma modulator was designed to be compatible with many mobile wireless standards. This modulator has a reconfigurable structure to adapt to various standards from 0.2 to 20 MHz. The designed modulator uses a VCO-based quantizer not only for lowering power consumption, but also for reducing the required chip area. The presented modulator can function with up to third order of noise shaping, or in a low power mode in which the loop filter is disabled and only the VCO-based quantizer is used. The proposed modulator was implemented and simulated in transistor level in 180 nm technology. This modulator can digitize at least seven standards (LTE (20 MHz)/WLAN/LTE (9 MHz)/WCDMA/UMTS/Bluetooth/GSM) with a favorable dynamic range (65---89 dB) and power consumption (9.1 mW---670 μW).

A 10.2 mW multi-mode continuous-time ΔΣ ADC with 70–87 dB DR and 0.7–10 MHz bandwidth for TD-SCDMA and LTE digital receivers

This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators' coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70---87 dB dynamic range, and 66---84 dB peak SNDR with 8.4---10.2 mW power consumption under 1.5 V power supply.