A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC

Abstract

A 4-bit, third-order, continuous-time $\Sigma \Delta$ modulator is presented for use in wireless communications systems. Based on small-signal noise models, analyses for reducing noise in the feedback digital-to-analog converter (DAC) are presented in detail. This enables easy performance/area optimization for the DAC unit elements and the RC noise filter in the DAC bias circuits. To obtain high linearity while simplifying the DAC design, circuit- and layout-level design techniques for minimizing switching time mismatches among and inside the DAC unit elements are presented. As a result, glitch-induced harmonic distortion is greatly reduced, requiring only a simple data-weighted averaging for the multibit DAC. In combination with multipath multistage op amps used to implement active-RC integrators, the presented techniques make it feasible to design a high-performance $\Sigma \Delta$ modulator with low power and small area, which is desired in many wireless communications systems. The experimental prototype, implemented in a 28-nm CMOS technology, achieves a 72.6-dB dynamic range, a 70.7-dB peak SNR, and a 70.1-dB peak signal-to-noise plus distortion ratio for a signal bandwidth of 20 MHz. The total power consumption is 6 mW from a 1- and 1.4-V supply, of which analog and digital circuits dissipate 4.5 and 1.5 mW, respectively. The total active area is 0.058 mm2.