Continuous-time Implementation Research Articles

Sampled-Data Steering of Unicycles via PBC

In this letter, on the basis of a recently proposed discrete-time port-Hamiltonian representation of sampled-data dynamics, we propose a new time-varying digital feedback for steering mobile robots. The quality of the proposed passivity-based control is validated and compared through simulations with the existing literature and the continuous-time implementation using the unicycle as a case study.

Q-Learning for Continuous-Time Linear Systems: A Data-Driven Implementation of the Kleinman Algorithm

A data-driven strategy to estimate the optimal feedback and the value function in an infinite-horizon, continuous-time, linear-quadratic optimal control problem for an unknown system is proposed. The method permits the construction of the optimal policy without any knowledge of the model, without requiring that the time derivatives of the state are available for the design, and without even assuming that an initial stabilizing feedback policy is available. Two alternative architectures are discussed: the first scheme revolves around the periodic computation of some matrix inversions involving the Q-function, whereas the second approach relies on a purely continuous-time implementation of some dynamic systems whose trajectories are uniformly attracted by the solutions to the above algebraic equations. Interestingly, the proposed strategy essentially constitutes a (direct) data-driven implementation of the celebrated Kleinman algorithm, hence subsuming the particularly appealing features of the latter, such as quadratic monotone convergence to the optimal solution. The theory is then validated by the means of practically motivated applications.

Sequence learning, prediction, and replay in networks of spiking neurons

Sequence learning, prediction and replay have been proposed to constitute the universal computations performed by the neocortex. The Hierarchical Temporal Memory (HTM) algorithm realizes these forms of computation. It learns sequences in an unsupervised and continuous manner using local learning rules, permits a context specific prediction of future sequence elements, and generates mismatch signals in case the predictions are not met. While the HTM algorithm accounts for a number of biological features such as topographic receptive fields, nonlinear dendritic processing, and sparse connectivity, it is based on abstract discrete-time neuron and synapse dynamics, as well as on plasticity mechanisms that can only partly be related to known biological mechanisms. Here, we devise a continuous-time implementation of the temporal-memory (TM) component of the HTM algorithm, which is based on a recurrent network of spiking neurons with biophysically interpretable variables and parameters. The model learns high-order sequences by means of a structural Hebbian synaptic plasticity mechanism supplemented with a rate-based homeostatic control. In combination with nonlinear dendritic input integration and local inhibitory feedback, this type of plasticity leads to the dynamic self-organization of narrow sequence-specific subnetworks. These subnetworks provide the substrate for a faithful propagation of sparse, synchronous activity, and, thereby, for a robust, context specific prediction of future sequence elements as well as for the autonomous replay of previously learned sequences. By strengthening the link to biology, our implementation facilitates the evaluation of the TM hypothesis based on experimentally accessible quantities. The continuous-time implementation of the TM algorithm permits, in particular, an investigation of the role of sequence timing for sequence learning, prediction and replay. We demonstrate this aspect by studying the effect of the sequence speed on the sequence learning performance and on the speed of autonomous sequence replay.

Unifying the mechanism of mitotic exit control in a spatiotemporal logical model.

The transition from mitosis into the first gap phase of the cell cycle in budding yeast is controlled by the Mitotic Exit Network (MEN). The network interprets spatiotemporal cues about the progression of mitosis and ensures that release of Cdc14 phosphatase occurs only after completion of key mitotic events. The MEN has been studied intensively; however, a unified understanding of how localisation and protein activity function together as a system is lacking. In this paper, we present a compartmental, logical model of the MEN that is capable of representing spatial aspects of regulation in parallel to control of enzymatic activity. We show that our model is capable of correctly predicting the phenotype of the majority of mutants we tested, including mutants that cause proteins to mislocalise. We use a continuous time implementation of the model to demonstrate that Cdc14 Early Anaphase Release (FEAR) ensures robust timing of anaphase, and we verify our findings in living cells. Furthermore, we show that our model can represent measured cell-cell variation in Spindle Position Checkpoint (SPoC) mutants. This work suggests a general approach to incorporate spatial effects into logical models. We anticipate that the model itself will be an important resource to experimental researchers, providing a rigorous platform to test hypotheses about regulation of mitotic exit.

A Simple Switching-Frequency-Regulated Sliding-Mode Controller for a VSI With a Full Digital Implementation

This article describes the design of a first-order sliding-mode controller for a voltage source inverter (VSI) operating at a fixed switching frequency. The proposal is simple, as it does not include any integral or resonant action in the switching function, and good results are obtained in terms of robustness, steady-state tracking error, fast transient response, and low total-harmonic distortion (THD). The implementation methodology using a microcontroller preserves all the benefits of a continuous-time implementation. Moreover, the article analyzes the sliding motion dynamics, and stability conditions are derived. Experimental results obtained with a 2.2-kW inverter show that fixed switching-frequency operation and robust output-voltage regulation with good performance indexes are achieved.

Analyzing the developmental relation of academic self-concept and achievement in elementary school children: Alternative models point to different results.

The association between academic self-concept and achievement is assumed to be reciprocal. Typically, the association is analyzed by variants of the classical cross-lagged panel model. Results with more recently developed methodological approaches, for example, the random intercept cross-lagged panel model, its continuous-time implementation, and the latent change score model, are not available so far. The present study aimed to test the association between reading self-concept and reading achievement with different models to evaluate whether positive cross-lagged effects can be demonstrated with the alternative models. Drawing on a sample of 2,014 elementary students from Grade 1 to Grade 4, results of alternative models yielded noticeable differences. Support for reciprocal effects between reading self-concept and reading achievement was found using the classical and the full-forward cross-lagged panel models. No such effects were found in the other models. Thus, the reciprocal effect model can be called into question for elementary schoolchildren. The results are discussed with regard to the theoretical assumptions and appropriate methodological approaches. (PsycINFO Database Record (c) 2019 APA, all rights reserved).

Dynamic Analysis of Hybrid Impulsive Delayed Neural Networks With Uncertainties.

Neural networks (NNs) have emerged as a powerful illustrative diagram for the brain. Unveiling the mechanism of neural-dynamic evolution is one of the crucial steps toward understanding how the brain works and evolves. Inspired by the universal existence of impulses in many real systems, this paper formulates a type of hybrid NNs (HNNs) with impulses, time delays, and interval uncertainties, and studies its global dynamic evolution by a robust interval analysis. The HNNs incorporate both continuous-time implementation and impulsive jump in mutual activations, where time delays and interval uncertainties are represented simultaneously. By constructing a Banach contraction mapping, the existence and uniqueness of the equilibrium of the HNN model are proved and analyzed in detail. Based on nonsmooth Lyapunov functions and delayed impulsive differential equations, new criteria are derived for ensuring the global robust exponential stability of the HNNs. Convergence analysis together with illustrative examples show the effectiveness of the theoretical results.

A Hybrid Multi-Path CMOS Magnetic Sensor With 76 ppm/°C Sensitivity Drift and Discrete-Time Ripple Reduction Loops

This paper presents a temperature-insensitive magnetic sensor system for contactless current measurements. To simultaneously achieve wide bandwidth and low noise, the proposed system employs a multi-path structure with a set of spinning current Hall sensors in its low-frequency path and a set of pick-up coils in its high-frequency path. The Hall sensors and pick-up coils are used in a differential sensing arrangement that naturally rejects common-mode magnetic field interference, e.g., due to the earth’s magnetic field. A common-mode ac reference field can then be used to continuously stabilize the sensitivity of the Hall sensors, which, unlike that of the pick-up coils, is quite temperature dependent. In this design, the ripple reduction loops in the Hall sensor readout are implemented in a discrete-time manner, and so occupy 20% less area than a previous continuous-time implementation. Over a −45 °C to 105 °C temperature range, the proposed system reduces the Hall sensor drift from 22% to 1%, which corresponds to a temperature coefficient of 76 ppm/°C.

Speech Processing on a Reconfigurable Analog Platform

We describe architectures for audio classification front ends on a reconfigurable analog platform. Real-time implementation of audio processing algorithms involving discrete-time signals tend to be power-intensive. We present an alternate continuous-time system implementation of a noise-suppression algorithm on our reconfigurable chip, while detailing the design considerations. We also describe a framework that enables future implementations of other speech processing algorithms, classifier front ends, and hearing aids.

High-level design of general multi-stage noise band cancellation $$\Upsigma\Updelta$$ Σ Δ ADC optimized for nonlinearly distorted signals

This article presents the high-level design of general multi-stage noise band cancellation (MSNBC) $$\Upsigma\Updelta$$ Σ Δ analog-to-digital converters (ADC). The MSNBC architecture enables to extend the conversion bandwidth of a primary modulator and to provide high resolution conversion. Moreover, this architecture should offer a low power consumption. This type of ADC is very useful for wideband and high resolution application such as the digitization of data for the linearization of base station (BTS) power amplifiers. This article introduces the MSNBC architecture and provides a methodology for the high-level design of such ADC for both discrete-time and continuous-time implementation. The methodology enables the design of stable and high resolution modulators and, the direct synthesis of digital FIR filters that are used for noise cancellation. This methodology is fast and useful to design high performance MSNBC $$\Upsigma\Updelta$$ Σ Δ ADC.

A Low-Power CT Incremental 3rd Order <formula formulatype="inline"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> ADC for Biosensor Applications

This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

On Continuous-Time Incremental $\Sigma\Delta$ ADCs With Extended Range

In this paper, the use of continuous-time implementation in extended-range (ER) incremental sigma-delta analog-to-digital converters is analyzed in order to explore a possible solution to low-power multichannel applications. The operation principle, possible loop filter topologies, and critical issues are considered using a general approach. It is demonstrated that, in order to fully benefit from ER, careful attention has to be paid to the analog-digital transfer function mismatches. A third-order single-bit topology validates the theoretical analysis. Its performance is evaluated while the impact of key circuit nonidealities is quantified through behavioral-level simulations. It is shown that, by applying analog-digital mismatch compensation in the digital domain, it is possible to relax the amplifiers' finite gain-bandwidth product and finite dc gain requirements, thus allowing a power-conscious alternative.

Tracking improves performance of biological collision avoidance models

Collision avoidance models derived from the study of insect brains do not perform universally well in practical collision scenarios, although the insects themselves may perform well in similar situations. In this article, we present a detailed simulation analysis of two well-known collision avoidance models and illustrate their limitations. In doing so, we present a novel continuous-time implementation of a neuronally based collision avoidance model. We then show that visual tracking can improve performance of these models by allowing an relative computation of the distance between the obstacle and the observer. We compare the results of simulations of the two models with and without tracking to show how tracking improves the ability of the model to detect an imminent collision. We present an implementation of one of these models processing imagery from a camera to show how it performs in real-world scenarios. These results suggest that insects may track looming objects with their gaze.

Tube-based robust sampled-data MPC for linear continuous-time systems

This note extends to the continuous-time case the “tube-based” approach for the design of discrete-time robust model predictive control (MPC) algorithms developed in Mayne, Seron, and Raković (2005). This extension is of interest in view of the simplicity and popularity of the method as well as of the industrial relevance of continuous-time implementations of MPC. The proposed robust control law is composed of two terms: (1) a sampled-data MPC control law and (2) a continuous-time state feedback term.

Fully Integrated CMOS EME-Suppressing Current Regulator for Automotive Electronics

In this paper, two circuit design techniques for lower electromagnetic emission (EME) are demonstrated based on shaping the supply current: 1) a discrete-time EME-SCR with a digital feedback loop to obtain more EME attenuation in the low frequency range starting from 150 kHz. It achieves maximum 30 dB di/dt reduction at high frequency with 60 μA quiescent current and a 230 pF on-chip capacitance. The cutoff frequency is shifted down to 100 kHz, which is about 10x lower compared with the continuous-time implementation. 2) The frequency modulation of the discrete-time EME-SCR's clock to further reduce the EME level in a wide frequency range. Measurement results show the effectiveness of these circuit techniques on the reduction of EME on chip level.

Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

This paper presents a new concept of multirate cascade <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulators, in which the signal is downsampled across the cascade instead of being upsampled as done in conventional multirate architectures. This strategy is suited for hybrid continuous-time/discrete-time cascade <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulators, where only the front-end stage is implemented by continuous-time circuits, and the remaining back-end stages are realized using switched-capacitor circuits. The main drawback of this approach comes from the implicit aliasing error signal due to the downsampling process. However, as shown in this paper, this error can be completely canceled in the digital domain, with no additional analog hardware required. The combination of these features results in a new class of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulators, which are potentially faster and more power efficient than conventional multirate architectures and more robust against circuit element tolerances than cascade single-rate continuous-time implementations for wideband applications.

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators

In cascaded ΔΣ modulators (DSMs), the quantization noise of the earlier stage leaks to the output unless completely cancelled by the digital noise cancellation filter (NCF). The noise leakage is worse in the continuous-time (CT) implementation due to the poorly controlled time constant of the analog loop filter. A parameter-based continuous-time to discrete-time transform is developed to get an exact digital NCF, and the analog filter time constant is calibrated to match with the digital NCF. A binary pulse tone is injected into the quantizer to detect the filter time-constant error, and eliminated by zero-forcing its residual power based on the adaptive least-mean-square (LMS) algorithm. A 2-1-1 cascaded CT-DSM prototype in 0.18-μm CMOS demonstrates that the spectral density of the leaked noise is lower than 10 nV/?Hz after the capacitors in the Gm-C loop filters are trimmed with 1.1% step. With a 1-Vpp full-scale input, it achieves a dynamic range of 68 dB within 18-MHz bandwidth at an over-sampling ratio of 10. The analog core and the digital logic occupy 1.27 mm2,and consume 230 mW at 1.8 V.

A Third-Order 9-Bit 10-MHz CMOS $\Delta \Sigma $ Modulator With One Active Stage

We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.

Welfare analysis of conditional indexation schemes from a two-reference-point perspective

AbstractConditional indexation has recently attracted interest with pension funds that are looking for a middle way between defined benefit and defined contribution. In this paper, we analyze conditional indexation schemes from a life-cycle investment perspective. Welfare analysis is applied to investigate the performance of such schemes relative to alternative investment strategies such as fixed-mix policies. We carry out this analysis in the context of a broad family of utility functions, which takes into account the possible presence of two benchmark levels corresponding to a minimum guaranty and to full indexation, respectively. For the purpose of comparability, we construct a self-financing continuous-time implementation of the conditional indexation scheme. The implementation involves continual adjustment of the parameters of the contingent claim representing final payoff. Our findings indicate that, in situations where large weight is placed on the benchmark levels, conditional indexation is fairly close to being optimal.

Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time Sigma-Delta Modulators

This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigmadelta (ΣΔ) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT ΣΔ modulator in a 1.2 V 130 nm CMOS technology.