Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

Abstract

This paper presents a new concept of multirate cascade <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulators, in which the signal is downsampled across the cascade instead of being upsampled as done in conventional multirate architectures. This strategy is suited for hybrid continuous-time/discrete-time cascade <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulators, where only the front-end stage is implemented by continuous-time circuits, and the remaining back-end stages are realized using switched-capacitor circuits. The main drawback of this approach comes from the implicit aliasing error signal due to the downsampling process. However, as shown in this paper, this error can be completely canceled in the digital domain, with no additional analog hardware required. The combination of these features results in a new class of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulators, which are potentially faster and more power efficient than conventional multirate architectures and more robust against circuit element tolerances than cascade single-rate continuous-time implementations for wideband applications.