Continuous-time Delta-sigma Modulator Research Articles

A Low-EMI Continuous-Time Delta-Sigma-Modulator Buck Converter With Transient Response Eruption Techniques

This article proposes a low spurious noise and fast-transient-response buck converter with second-order continuous-time delta-sigma modulator (CT-DSM). The DSM technique has the superiority of oversampling and the characteristics of noise shaping to reduce spurious noise and speed up transient response. Moreover, the transient response eruption technique uses a dynamic current compensator to accelerate the transient response. Therefore, the proposed CT-DSM buck converter reduces spurious noise, reduces the output harmonic tones, and accelerates transient response, but it keeps high efficiency, low noise, and low ripple of the traditional switching converter. The proposed DSM buck converter is fabricated in TSMC 0.35 μm 2P4M CMOS process with a chip area of 1.32 ×1.38 mm. The measurement results show that the peak noise power is -70 dBm across output spectrum, which is -10 dBm lower than a traditional CT-DSM buck converter. When the load current changes from 50 to 500 mA and from 500 to 50 mA, the transient responses are both 4 μs, which are 7 μs faster than the traditional CT-DSM buck converter. The maximum output overshoot voltage is 20 mV, the output voltage ripple is 10 mV, and the conversion peak efficiency 90.4% at the output voltage of 2.4 V. These characteristics keep the same performances as or even better than the traditional CT-DSM buck converter.

Techniques for Sigma Delta ADC Design using CMOS Technology for CODEC

This paper presents the careful study of sigma-delta analog to digital convertor. The operations, characterizing parameters and totally different structures projected square measure conferred in basic type. the varied techniques and strategies for the design of a CMOS 3rd order Continuous Time (CT) Sigma Delta (SD) Modulator, where in to enhance the gain of the loop filter and to avoid the loading effect of the succeeding stage, facile differential pairs square measure enclosed between the passive RC integrators. then the ADC are optimized victimization Genetic Algorithms so as to realize the nice exchange between RC variations and loop stability.This makes SD-ADC more advantageous compared to conventional converters, that makes possible to use this SD-ADC in bio-medical applications

Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators

Chopping is an efficient way of mitigating the effect of flicker noise in continuous-time delta-sigma modulators (CT ${\Delta \Sigma }$ Ms). Unfortunately, chopping causes the demodulation of shaped quantization noise into the signal band. Prior works have analyzed noise-folding effects in chopped integrators that use single-stage and two-stage feedforward-compensated OTAs. These works use restrictive assumptions, such as settling of the OTA internal nodes at the chopping instants, and an NRZ feedback DAC waveform. This paper gives a general model for aliasing of shaped noise in a chopped integrator that incorporates arbitrary OTAs, arbitrary DAC pulse-shapes, and incomplete settling. Using the theory of linear periodically time-varying (LPTV) systems, we derive a simple simulation test-bench that can be used to estimate the parameters of our model. Thanks to this, the effects on chopping on the performance of the modulator can be rapidly estimated without running long transient simulations. Simulation and experimental results that support our theory are given.

A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator

A 4-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) is described. The CT-SDM employs a stochastic quantizer consisting of 63 comparators whose random input offset provides linear multi-bit quantization. The output of the stochastic quantizer is accumulated by a digital accumulator before feeding it back to the input of the loop filter of the CT-SDM, which greatly improves the linearity of the stochastic quantization. The CT-SDM implemented in a 65-nm CMOS technology shows the peak signal-to-noise+distortion ratio of 72.5-dB while consuming 3.6-mW from a 0.9-V supply.

A 20‐MHz bandwidth, 75‐dB dynamic range, continuous‐time delta‐sigma modulator with reduced nonidealities

SummaryThis letter presents a 4‐bit continuous‐time delta‐sigma modulator (CT‐DSM) fabricated using a 65‐nm CMOS process. The circuit is designed for wide‐bandwidth applications, such as those related to wireless communications. This CT‐DSM has an oversampling ratio of 16 with a 640‐MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn‐to‐zero (NRZ)–type pulse, whereas the second DAC pulse is a return‐to‐zero (RZ)–type pulse; this is accomplished using a current‐steering DAC. In order to reduce mismatch without using a data‐weighted averaging circuit, the size and layout of the unit current source in the current‐steering DAC are considered carefully. The CT‐DSM achieves a signal‐to‐noise ratio (SNR) of 67.3 dB, a signal‐to‐noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20‐MHz signal bandwidth.

A Wide Dynamic Range Multi-Mode Band-Pass Continuous-Time Delta–Sigma Modulator Employing Single-Opamp Resonator With Positive Resistor-Feedback

In this brief, we present a wide dynamic range (DR) multi-mode band-pass continuous-time delta–sigma modulator (BP-CTDSM) employing a single-opamp resonator with positive resistor-feedback. The positive resistor-feedback single-opamp resonator achieves high quality factor even if an opamp has lower gain-bandwidth. The prototype BP-CTDSM is fabricated in a 180-nm CMOS technology. The signal bandwidth is 200 kHz and the DRs of 90.39, 88.42, and 88.15 dB are achieved at the center frequencies of 20, 5, and 2 MHz, respectively.

Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator’s loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC’s disadvantageous trade-off between the modulator’s jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM’s loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable.

Effect of supply scaling on noise performance of 0.6–1.2 V continuous‐time delta‐sigma modulator

The dependence of the noise performance of a 0.6–1.2 V continuous-time delta-sigma modulator (DSM) on its supply voltage is analysed. The noise performance and benchmark figure of merit (FoM) mainly depend on the power dissipation, thermal noise contributions from the analogue loop filter, and the quantisation noise from the quantisers. Theoretical estimates for the supply dependence of loop noise and quantisation noise, and their respective FoM are derived and verified with simulations for a 2 MHz third-order continuous-time DSM, while operating from a supply between 0.6 and 1.2 V. At a larger supply voltage, the FoM related to the loop filter noise improves, whereas at lower supplies, the FoM related to the quantisation noise improves. As a result, the overall FoM of the DSM reaches an optimum at a particular supply. The supply voltage with the best FoM of the DSM is derived with the supply-scaling FoM of the loop filter and quantisers. For an equal FoM of the loop filter and quantisers at a supply V DD , 0 , the optimal supply voltage is 0.66 V DD , 0 .

An Energy-Efficient 3.7-nV/<inline-formula> <tex-math notation="LaTeX">$\surd$ </tex-math> </inline-formula>Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme

This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CT $\Delta \Sigma \text{M}$ ). By exploiting the CCIA’s ability to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/ $\surd $ Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa ( $1\sigma$ ) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by $80\times $ over a 50 °C range.

Clock Jitter Analysis of Continuous-Time <inline-formula> <tex-math notation="LaTeX">$\Sigma\Delta$ </tex-math> </inline-formula> Modulators Based on a Relative Time-Base Projection

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma-delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based ΣA modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.

An Extremely Linear Multi-Level DAC for Continuous-Time Delta-Sigma Modulators

The nonlinearity of the multi-level digital-to-analog converter (DAC), arising from element mismatches, is a critical issue in the design of multi-bit Delta-Sigma modulators (DSMs). In this brief, we propose an extremely linear multi-level DAC that requires no trimming, calibration, or dynamic element matching for continuous-time DSMs that are sensitive to loop delays. The proposed DAC combines a tri-level switched-capacitor circuit with a pulse-width-modulation (PWM) scheme modified to eliminate the nonlinearity-causing signal-dependent timing of the PWM pulses. Theoretical analysis and Monto-Carlo simulations verifying the linearity of the proposed DAC are presented.

A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA

This brief presents the design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator. Using a customized digital integrator with inherent data-weighted averaging at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the modulator robustness to the out-of-band blocker is improved by increasing the number of levels in the digital integrator and feedback DACs. The out-of-band blocker tolerance is improved by 3 dB compared to a conventional CIFF-B delta-sigma modulator with a minimal increase in the power consumption. The proposed architecture has been implemented in a 65-nm CMOS technology and operates at a 250 MHz sampling frequency. It achieves 73.5 dB SNR, 72.4 dB SNDR, and 92 dB SFDR over a 7-MHz bandwidth and a Walden figure-of-merit of 341 fJ/conversion.

A second-order continuous-time delta-sigma modulator with double self noise coupling

In this paper, a second-order continuous-time delta-sigma modulator using double self noise coupling technique is proposed. Noise coupling increases the effective order of the noise shaping loops. The presented architecture splits the outputs of the quantizer into a most significant bit segment (MSBs) and a least significant bit segment (LSBs). The LSBs can be viewed as the residue after the MSBs quantization and is fed back to the front of the quantizer and the second integrator respectively, as a result, double self noise coupling is achieved. In addition, the quantizer also provides a convenient means to incorporate the excess-loop-delay compensation. As a result, the digital noise cancellation logic complexity is simplified, the digital and analog filter mismatch is relaxed, meanwhile, it strictly suppresses the noise within the effective signal bandwidth by reducing the main MSBs mismatch. Finally, the resolution is increased, the hardware complexity and the output swing of the integrator are reduced, which greatly relaxes the bandwidth and gain requirement of the Op-Amp design. The higher order noise shaping introduced by the residue of multi-bit quantizer further reduces the quantization noise.

Design challenges for a new mostly digital VCO‐based delta‐sigma modulator

This study presents an architecture and study of closed-loop continuous time delta-sigma modulation utilising only voltage-controlled oscillators (VCOs) and digital elements. It incorporates a VCO-based integrator in which the offset due to the carrier frequency ( f c ) is digitally subtracted. Unlike some prior structures, an extra VCO for reference signal generation is not necessary which can lead to a reduction in power consumption, area and noise. In addition, in comparison to a recently reported structure, the VCO is placed inside the feedback loop, so the input signal swing of the VCO is decreased and the linearity is improved. However, the proposed structure suffers from two noise folding effects at low frequencies which degrade the dynamic range of the modulator. These two noise folding effects will be analysed and it will be shown that these problems can be tackled by the right choice of f c and appropriate design. Behavioural simulations are done for the proposed structure to confirm the structure's performance.

Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI

Recent progress in continuous-time (CT) Delta-Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.

A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO

This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO’s input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO’s input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1-dB dynamic range in 480 kHz–20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors’ best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.

Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator

The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp’s requirements including dc gain, unity gain bandwidth, thermal and 1/ ${f}$ noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 $\mu \text{W}$ from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 $\mu \text{W}$ from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

Calibration is preferred over dynamic element matching (DEM) techniques to correct nonlinearity in digital-to-analog converters (DACs) in high-speed multi-bit continuous-time (CT) delta-sigma modulators (DSMs) to avoid introducing extra excess loop delay. The state-of-the-art calibration techniques, however, involve substantial external control, making it difficult for a complete on-chip realization. In this paper a highly automated on-chip technique for calibrating differential nonlinearity (DNL) and inter-symbolinterference (ISI) errors of a multi-bit DAC in a CTDSM is presented. The proposed technique implements a Calibration Control System (CCS), equipped with a Finite State Machine (FSM) logic, that automates the entire calibration process with minimal intervention. The calibration loop utilizes the modulator itself to produce the digital estimates of the DNL and the average ISI errors of each unit element of the DAC. These digital estimates are then used to configure auxiliary DACs for correction of the errors in the main DAC. For every unit element in the main DAC, an 8-bit dynamic auxiliary DAC injects a calibrated compensation current in the loop at every up-transition of the input data to cancel the average ISI error, and a 5-bit constant current source array corrects its DNL error. Design considerations and post-layout simulation results for a 50-MHz bandwidth, 1.8GS/s 4 th -order CTDSM are presented. The modulator has a 4.8 dB and a 10.8 dB improvement in SNDR and SFDR respectively with calibration, leading to a dynamic range of 71 dB with a total power consumption of 37.7 mW from 1.3 V and 1 V supplies.

Closed-Form Distortion Formulas for Continuous-Time Sigma-Delta Modulators

Closed-form harmonic distortion (HD) formulas are derived by a symbolic tool for continuous-time Sigma-Delta modulators (CTSDMs). Distortion caused by operational amplifiers (Opamps) inside active-RC integrators is analyzed by the Volterra series method. Using the closed-form formulas the third order HD factor (HD3) can be calculated directly without the need of running conventional behavioral simulation. Application of the closed-form formulas to distortion optimization is discussed.

Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ( $\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB.