Continuous-time Delta-sigma Modulator Research Articles

Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs

We present design techniques for single-bit continuous-time delta–sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB.

A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm2 while achieving input-referred noise levels of 6.26 and 3.54 µVrms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mVpp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces.

Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators

This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling

A hybrid noise-coupling (HNC) technique is proposed to mitigate the issues with a digital noise-coupling (DNC) structure. In the proposed technique, the unwanted quantization noise that is generated from the noise-coupling analog-to-digital converter (ADC) is injected into the input of the quantizer with one-clock cycle delay, thus increasing the order of noise-shaping of this error. Behavioral simulation shows that the HNC is highly robust against gain variation. The proposed fourth-order continuous-time (CT) delta-sigma modulator (DSM) with HNC scheme was designed in a 28-nm CMOS technology with a core size of 0.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With an oversampling ratio (OSR) of 32, the proposed design achieves a signal-to-noise-distortion ratio (SNDR) of 97.20-dB at a signal bandwidth of 15.625-kHz, which has a 7-dB improvement in comparison to DNC only without introducing significant hardware complexity.

Time-domain Continuous-time Delta-sigma Modulator using VCO-based Integrator and GRO-based Quantizer

This paper presents a 3SUPrd/SUP-order time-domain continuous-time delta-sigma modulator (CTDSM) using two voltage-controlled oscillator (VCO)-based integrators and a gated ring oscillator (GRO)-based quantizer. The GRO-based quantizer has 1SUPst/SUP-order noise-shaping characteristics without the increase of the signal transfer function (STF) order and has magnificent linearity. Also, the output of the GRO-based quantizer has an intrinsic data weighted averaging (DWA)-based dynamic element matching (DEM) pattern that is less susceptible to the DAC mismatch. The PWM signal, which is the input of the GRO-based quantizer, is generated by the VCO-based integrator without additional blocks. In the pre-layout simulation, the CTDSM consumes 3.84 mW and achieves an SNDR of 71.2 dB at a 400-MSs sampling frequency and a 10-MHz bandwidth.

Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review

The maximum sampling frequency of oversampled continuous-time (CT) delta-sigma modulators (DSM) has increased considerably over the past decade. Plus, with its implicit anti-aliasing filtering and resistive input impedance, it results in a substitution of discrete-time pipeline ADCs in wireless receivers. For CT DSMs, multi-stage noise-shaping (MASH) topology features a cascade of low-order loops, thus allowing the exploration of larger sampling rate when compared with a single-loop topology. However, the inherent quantization noise (QN) leakage constrains the achievable resolution of the MASH DSM. Besides, the QN extraction of preceding stages is problematic in CT MASH with very fast sampling rates. This brief review the fundamentals and design considerations of CT MASHs. It highlights recent state-of-the-art CT MASH addressing the above design challenges, including architectural advances, circuitry innovation and digital calibration. This brief intends to serve as a starting point in the forthcoming development of a wideband low-power CT MASH DSM.

Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback

High-resolution continuous-time delta-sigma modulators use resistive feedback DACs for low-noise operation. Such DACs have conventionally been switched at the reference end. It turns out that reference-path resistance degrades the performance of these DACs. This problem can be addressed by the virtual-ground-switched resistor DAC. However, moving the switches to the virtual-ground-side degrades alias-rejection of the modulator. This brief analyzes the mechanism of degradation and develops a model to estimate alias rejection. Our theory is supported by simulations and measurements from a prototype modulator designed in a 180nm CMOS process. We then describe a way to address this problem, and demonstrate its efficacy using layout-extracted simulations.

A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator

This brief presents a continuous-time sigma-delta modulator with a new integrator design based on continuous-time delays. It eliminates the need for high gain amplifiers, while providing loop gain for the modulator. It can also intrinsically compensate for the excess loop delay without additional feedback paths. The proposed integrator enables a compact modulator design that can operate under low supply voltages with high power efficiency for better process scalability. A 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order modulator prototype was fabricated in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\mu }\text{m}$ </tex-math></inline-formula> CMOS. Measurement results show that it has 66dB dynamic range and 60dB SNDR over 4MHz signal bandwidth at 500MHz sampling frequency, while dissipating 1.92mW from a 1.4V supply. A FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> of 286 fJ/conversion is achieved. It only occupies 0.039 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area.

A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection

A multi-level DAC with high intrinsic linearity and low power consumption enables a greater design space for wide-band continuous-time (CT) Delta-Sigma modulators (DSMs). This manuscript introduces an intrinsically highly linear 5-level switched-capacitor (SC) DAC with a power-saving charge recycling technique for wideband CT DSMs. We also adopt a distinct modulator architecture that places a large low-pass filter (LPF) capacitor at the input of the first amplifier. This architecture substantially enhances the modulator’s power efficiency and restores the modulator’s alias rejection ratio (AR) in the presence of an SC type of DAC. To validate the proposed techniques, a DSM prototype with a 10-MHz bandwidth and 800 MHz sampling rate (fs) is fabricated in a 65-nm CMOS technology. Consuming 1.3 mW from a 1.2-V supply, the prototype achieves a peak signal-to-noise-plus-distortion ratio of 72.3 dB and a dynamic range of 73.3 dB in experiments. The corresponding Warden’s and Schreier’s figures of merits are 19.3 fJ/conv-step and 171.2 dB, respectively. The measured ARs are 52.7 dB and 54.3 dB at fs and 2fs, respectively. The DSM further tolerates an rms clock jitter of 11 ps.

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp

This paper proposes a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

A New Improved Second-Order Delta-Sigma-Modulation Buck Converter With Low-Noise and Transient-Acceleration Loops

In this article, we propose a new improved fast-transient-response and low-noise high-efficiency buck converter with second-order continuous-time delta-sigma-modulation (CT-DSM) techniques. First, by utilizing the oversampling theorem and noise-shaping technique with the second-order delta-sigma modulation, the output noise within the bandwidth can be reduced effectively. Second, the adding of the transient acceleration loop not only can improve the transient recovery time when the load current changed but also lowers the undershoot and overshoot voltage. Third, a rail-to-rail operational transconductance amplifier without voltage dividers is employed in the proposed converter, which helps sensing the inductor current, moving the inductor pole to a high frequency, speeding up the transient response, and stabilizing the proposed converter modules. Finally, the proposed converter has been implemented with TSMC 0.18 μm 1P6M process and occupies an area of 1.19 × 1.19 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When the load current changed from 50 to 500 mA and 500 to 50 mA, the transient recovery time was both 4 μs, which improved 8 and 16 μs than the traditional CT-DSM converter. The output voltage ripples are kept under 13 mV and the overshoot and undershoot voltage is 20 and 14 mV, respectively. The measured output-to-noise ratio is 80.7 dB, with the sampling frequency of 10 MHz. The peak efficiency is 92.1%, at the output voltage of 2.5 V and load current of 150 mA.

Modelling an oscillator phase noise whose spectral density contains both 1/f 2 and 1/f 3 regions

This paper introduces a new equation for modelling the phase noise spectrum of an oscillator. The new equation can model both of 1/f2 and 1/f3 regions in a phase noise spectrum. To verify the model and show its effectiveness, a mathematical analysis is performed on the effect of the oscillator phase noise on the performance of a continuous-time delta-sigma modulator. By comparing the results from the mathematical analysis with those from the Simulink simulation results, it is shown that using the proposed equation can properly predict the effect of oscillator phase noise on the modulator performance.

A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM

A continuous-Time delta-sigma modulator (CT-DSM) excels at high-bandwidth (BW), high-dynamic-range analog-to-digital conversion. However, CT-DSMs suffer from PVT variation, high sensitivity to timing errors, and are restricted in sampling rate. This work proposes a hybrid-loop (HL) DSM architecture to mitigate the disadvantages of CT-DSM while providing similar performance. This work also introduces a bandpass time-interleaved noise-shaping (TINS) successive-approximation (SAR) architecture, which increases the sampling rate of TINS SAR. A prototype HL-DSM with bandpass TINS-SAR quantizer is built in 28-nm CMOS and occupies a die area of 0.09 mm². The measured peak SNDR is 67.5 dB for a 100-MHz BW. The total power consumption is 13.4 mW at a sampling rate of 1.6 GS/s. The resulting Schreier FoM of 166.2 dB is comparable to state-of-the-art CT-DSM converters.

A 30.3 fA/√Hz Biosensing Current Front-End With 139 dB Cross-Scale Dynamic Range.

This paper presents an 8-channel array of low-noise (30.3 fA/√Hz) current sensing front-ends with on-chip microelectrode electrochemical sensors. The analog front-end (AFE) consists of a 1st-order continuous-time delta-sigma (CT ΔΣ) modulator that achieves 123 fA sensitivity over a 10 Hz bandwidth and 139 dB cross-scale dynamic range with a 2-bit programmable current reference. A digital predictor and tri-level pulse width modulated (PWM) current-steering DAC realize the equivalent performance of a multi-bit ΔΣ in an area- and power-efficient manner. The AFE consumes 50.3 µW and 0.11 mm2 per readout channel. The proposed platform was used to observe protein-ligand interactions in real-time using transient induced molecular electronic spectroscopy (TIMES), a label- and immobilization-free biosensing technique.

Power Electronics Programmable Voltage Source with Reduced Ripple Component of Output Signal Based on Continuous-Time Sigma-Delta Modulator

In this work, an idea of a wideband, precision, power electronics programmable voltage source (PVS) is presented. One of the basic elements of the converter, the control section, contains a continuous-time sigma-delta modulator (SDM) with a pair of interconnected complementary comparators, which represents a new approach. In this case, the SDM uses comparators with a dynamic hysteresis loop (DHC) that includes an AC circuit rather than an R-R network. Dynamic hysteresis is a very effective way of eliminating parasitic oscillation during the signal transition at the input of the comparator; it also affects the frequency characteristics and, especially, the phase properties of the comparator, and this phenomenon is exploited in the proposed converter. The main disadvantage of all pulse-modulated converters is the presence of a ripple component in the output voltage (current), which reduces the quality of the output signal and may cause high-frequency disturbances. A basic feature of PVS is a lower RMS value for the pulse modulation component in the output voltage of the converter, compared to the typical value. Another important feature of the proposed converter is the ability of precise mapping of the output voltage to the reference (input) signal. The structure of the control circuit is relatively simple—no complex, digital components are used. Due to the high frequency of the SDM output bit-stream, the simulation model of the power stage of PVS is based on the power modules with gallium-nitride field effect transistors (GaN FETs). The work discusses the rules of PVS operations and the results from PVS simulation model studies as well as highlights the possible application fields for systems with a PVS.

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

This paper presents a low-power second-order continuous-time (CT) Delta-Sigma Modulator (DSM) using a new design methodology for biomedical applications. The proposed design methodology first implements a target block with the highest power consumption at a transistor level before optimizing the DSM coefficients. We are also able to reduce the area usage by appropriate limitations on the DSM range in the proposed design process. The DSM was implemented using the genetic algorithm (GA) and appropriate chopping techniques in our design process. The design was implemented in 0.18um CMOS technology by using a 0.083 mm2 layout, with a maximum SNDR and dynamic range of 94.28 and 100 dB, respectively, for a 2 kHz bandwidth and 32.34uW power consumption.

전압 제어 발진기 기반 연속시간 시그마 델타 모듈레이터 아날로그-디지털 변환기

VCO(voltage controlled oscillator)를 기반으로 연속시간 시그마 델타 모듈레이터를 구현하는 것은 반도체 공정이 발달할수록 확실한 이점을 얻을 수 있다. VCO는 기본적으로 인버터를 기반으로 구현되기 때문에, 반도체 공정 발달에 따라 그 속도가 증가하기 때문이다. 또한 VCO는 시간 영역에서 동작하기 때문에, 공정 발달에 따른 동작 전압 영역이 낮아지더라도 충분히 넓은 dynamic range를 유지할 수 있는 장점이 있다. 이러한 장점들은 VCO 기반 연속시간 시그마-델타 모듈레이터 아날로그-디지털 변환기 구현에 충분히 매력적으로 다가올 수 있다. 본 논문은 VCO 기반 연속시간 시그마-델타 모듈레이터 아날로그-디지털 변환기는 28㎚ CMOS 공정 모델을 사용하여 구현했다. 모델링 시뮬레이션 결과를 토대로 1.6㎓ 샘플링 클록을 이용하여 80㎒의 대역폭과 70.0㏈의 peak 노이즈-왜곡 대비 신호 크기를 가지는 것을 확인했다.

Five‐level class‐D amplifier employing fourth‐order continuous‐time sigma‐delta modulator

A new closed-loop multi-level Class-D amplifier employing a fourth-order ‘continuous-time sigma-delta modulator’ is proposed and analysed. The proposed amplifier is intrinsically linear and it has approximately the fixed ‘total harmonic distortion plus noise’ against the input frequency. The corresponding circuit is designed and simulated in 180 nm technology (3.3 V), while the post-layout model of the power stage is employed. A total harmonic distortion plus noise of 0.0016%, the quiescent current of 2.6 mA, the maximum efficiency of 94%, the average switching frequency of 400∼500 kHz and an excellent ‘power supply reject ration’ of 120 dB are achieved.

A 0.6-V 86.5-dB DR 40-kHz BW Inverter-Based Continuous-Time Delta–Sigma Modulator With PVT-Robust Body-Biasing

This letter presents a low-power continuous-time delta-sigma modulator (CTDSM) that operates at a 0.6 V supply. The loop filter of the CTDSM is realized with inverter-based integrators and negative-R compensation on each integrator’s virtual ground. A body-biasing technique is used for inverters as well as for negative-Rs to ensure robustness against process, voltage, and temperature (PVT) variations. A prototype CTDSM is fabricated in a 28 nm CMOS process, and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 W from a 0.6 V supply. This corresponds to the state-of-the-art Schreier FoM of 177.3 dB.

A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers

This article presents a circuit technique to improve the power efficiency of the well-established active-RC continuous-time (CT) Delta-Sigma modulator (DSM). The technique is to add a large capacitor at the virtual ground node of the first amplifier in an active-RC DSM. Without attenuating the in-band signal, this capacitor smooths out the fast transitions in the feedback and suppresses most of the quantization noise before processing by the first amplifier. The transconductance and output swing requirements of the crucial first amplifier can therefore be significantly relaxed. In addition, the technique converts an undesired parasitic pole into a desired one of the loop filter, reducing an amplifier and eliminating the problems associated with the parasitic pole. Last, the large capacitor at the virtual ground node opens a way to reduce the flicker noise because it allows the first amplifier to use large-sized input transistors without performance penalties. To verify the technique, a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order 1-bit active-RC DSM is designed and fabricated in 180-nm CMOS technology. Clocked at 320 MHz, it achieves a measured signal-to-noise-plus-distortion ratio of 78.7 dB over a 2 MHz bandwidth and a spurious-free dynamic range of 88.4 dB while consuming 0.59 mW, of which the first amplifier takes only 13.5%. The recorded Warden's and Schreier's figure of merits are 20.1 fJ/conv-step and 174 dB respectively. The proposed simple circuit technique makes this otherwise ordinary active-RC modulator one of the most power-efficient CT DSMs.