Constant Current Stress Research Articles

Time-dependent dielectric breakdown of MgO magnetic tunnel junctions and novel test method

Time-dependent dielectric breakdown (TDDB), which is used to measure reliability, depends on both the thickness of the tunnel barrier and bias voltage. In addition, the heat generated by self-heating in a magnetic tunneling junction (MTJ) affects TDDB. Therefore, we investigated TDDB with the self-heating effect for a MgO tunnel barrier with thicknesses of 1.1 and 1.2 nm by the constant voltage stress (CVS) method. Using the results of this experiment, we predicted a TDDB of 1.0 nm for the tunnel barrier. Also, we suggested the use of not only the CVS method, which is a common way of determining TDDB, but also the constant current stress (CCS) method, which compensates for the disadvantages of the CVS method.

Lowering the effective work function via oxygen vacancy formation on the GeO2/Ge interface

The use of a GeO2 interfacial layer (IL) between a high-k dielectric and a Ge substrate helps to reduce the interface state density in Ge MOS devices. We report that the presence of the GeO2 IL changes the effective work function (eWF) of the gate stack when annealed after high-k dielectric deposition. The eWF is reduced from 4.31eV to 3.98eV for TaN and from 5.00eV to 4.44eV for Ni. Consequently, the threshold voltage (Vth) decreases from 0.69V to 0.21V for Ni after post deposition annealing. Our investigation confirms that the generation of oxygen vacancies in the GeO2 IL near the Ge substrate is the main cause of the eWF modulation. In addition, the reliability of the GeO2 IL is investigated via the conductance method and a constant-current stress test.

Defect-Related Degradation of AlGaN-Based UV-B LEDs

This paper describes an extensive analysis of the degradation of (InAlGa)N-based UV-B light-emitting diodes (LEDs) submitted to constant current stress. This paper is based on combined electrical characterization, spectral analysis of the emission, deep-level transient spectroscopy (DLTS) and photocurrent (PC) spectroscopy. The results of this analysis demonstrate that: 1) UV-B LEDs show a gradual degradation when submitted to constant current stress; the decrease in optical power is stronger for low measuring current levels, indicating that degradation is related to the increase in Shockley–Read–Hall (SRH) recombination; 2) the current–voltage characteristics measured before/during stress show an increase in the current below the turn-on voltage, that is ascribed to the increase in trap-assisted tunneling (TAT) components; and 3) DLTS analysis and PC spectroscopy measurements were carried out to identify the properties of the defects responsible for the degradation of the optical and electrical characteristics. The results indicate that stress induces or activates defects centered around 2.5 eV below the conduction band edge. These defects, close to midgap, can explain both the increased SRH recombination and the increase in TAT components detected after stress. Moreover, the DLTS measurements allowed to identify the signature of Mg-related acceptor traps.

Application of Photocurrent Model on Polymer Solar Cells Under Forward Bias Stress

We performed a constant current stress at forward bias on organic heterojunction solar cells. We measured current voltage curves in both dark and light at each stress step to calculate the photocurrent. An existing model applied to photocurrent experimental data allows the estimation of several parameters such as generation, recombination, dissociation rate, and nearly zero field voltage within the active layer as a function of the stress time. The analysis of extrapolated parameters shows that the stress mainly affects the recombination rate of the polaron charge transfer states.

Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (tBD) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the tBD values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO2 was observed between 27 and 225 °C.

Long-Term Stability of Epitaxial (Nd 1– x Gd x 2 O 3 Thin Films Grown on Si(001) for Future CMOS Devices

The (Nd1– x Gd x )2O3 thin films were grown on Si(001) in 2005 using molecular beam epitaxy followed by an in vacuo metallization of Pt contacts. Pt/(Nd1– x Gd x )2O3/Si(001) metal-oxide-semiconductor structures have been characterized several times over the period of 2005–2015 in order to investigate the stability of their physical and electrical properties. Core-level X-ray photoelectron spectroscopy (XPS) spectra remeasured during 2015 depict that the layer still retains its original properties that were measured in 2005. Although there has been some degradation of electrical properties such as capacitance and leakage current over several years, interestingly the midgap density of interface traps’ ( $D_{{\mathrm{it}}})$ value has been found to be decreased from $1.1 \times 10^{12}$ to $3.5 \times 10^{11}$ eV $^{-1}$ cm $^{-2} $ over the years. The formation of silicate-like interface inferred from XPS measurements can be attributed to such an improvement over this period. Time-dependent dielectric breakdown measurements under constant current stress and constant voltage stress were also carried out to investigate the reliability of the structure.

Online state of charge estimation of lithium-ion batteries: A moving horizon estimation approach

Online state of charge (SOC) estimation of lithium-ion batteries (LIBs) relies not only on accurate battery model but also on effective state estimation method. In this study, a nonlinear battery state-space model based moving horizon estimation (MHE) approach is proposed to estimate SOC within the full range. The relationship between SOC and circuit parameters in battery model is captured by polynomial functions. The essential arrival cost in the MHE problem formulation is approximated by the filtering scheme and its covariance matrix is updated by extended Kalman filter (EKF) method. Hybrid pulse power characterization test is first used to guide battery model construction and tuning parameters determination in MHE. The constant current discharge test and dynamic stress test are then used to validate the applicability of the MHE and investigate the performance comparisons between MHE and EKF. The results demonstrate that compared to the EKF, the MHE is less sensitive to the poor initial SOC guesses and has faster convergence to the true SOC. The results thus validate that the MHE provides a potential promising approach to perform accurate, reliable and robust SOC estimation of LIBs.

Degradation of UV-A LEDs: Physical Origin and Dependence on Stress Conditions

This paper presents an extensive analysis of the degradation of UV-A light-emitting diodes (LEDs) submitted to constant current stress. The study is based on combined electrical, optical, and thermal measurements and demonstrates the following results: 1) the UV-A LEDs submitted to constant current stress show a gradual degradation, and the degradation rate is strongly dependent on the emission wavelength; 2) the degradation process is ascribed to the generation of point defects within the active region of the devices, with a subsequent increase in the nonradiative recombination rate; and 3) the time to degradation is strongly dependent on the stress current level and is thermally activated (activation energy equal to 0.36 eV).

Failure Analysis of a SiC MOS Capacitor with a Poly-Si Gate Electrode

The failure mechanism of a SiC metal-oxide-semiconductor capacitor with a poly-Si gate electrode was investigated by time-dependent dielectric breakdown testing under a 200-nA constant current stress. The capacitor exhibited both hard and soft breakdowns. After dielectric breakdown in both cases, adjacent concaves were observed on the capacitor with a field-emission scanning electron microscope. Additional optical beam-induced resistance changes and photo-emission analysis of a capacitor after hard-breakdown located a failure point on the periphery of a group of adjacent concaves. Cross-sectional scanning transmission electron microscope observation revealed that a narrow, vertical defect had formed at this point on the SiC substrate.

High-κ NdTaO4 dielectrics deposited on polycrystalline silicon substrates

High-k NdTaO4 dielectrics annealed with various temperatures were first deposited on polycrystalline silicon substrates. Material and electrical characterizations were performed. To examine the crystalline structures, X-ray diffraction patterns were analyzed. Electrical measurements including current–voltage characteristics, constant current stress, and the Weibull plots show that annealing could enhance the breakdown voltages, lower the trapping rate, and strengthen the reliability. Results indicate that annealing at 900 °C may optimize the dielectric performance. This dielectric shows promise for future gate material or flash memory integrated with current NdTaO4-based optical devices.

Reliability of InAs/GaAs Quantum Dot Lasers Epitaxially Grown on Silicon

We present the first reliability study of InAs/GaAs self-assembled quantum dot lasers epitaxially grown on Ge/Si substrates. Some devices maintain lasing oscillation after more than 2700 h of constant current stress at 30 °C, longer than any previous life tests of GaAs lasers epitaxially grown on silicon. No catastrophic failures were observed. The lasers were characterized to gain insight on the aging mechanism.

A study of trap-limited conduction influenced by plasma damage on the source/drain regions of amorphous InGaZnO TFTs

This study investigated electrical characteristics and stability variations of amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) with plasma damage on their source/drain (S/D) regions. The influence of the plasma damage on the TFT performance is absent as the channel length is 36–100 μm. When the channel length is decreased to 3–5 μm, the mobility () of the bottom gate TFT (BG TFT) with plasma damage is significantly degraded to 0.6 cm2 (V s)−1, which is much lower than 4.3 cm2 (V s)−1 of a damage-free BG TFT. We utilized the TFT passivation layer and the indium tin oxide (ITO), which was used as the pixel electrode material in the TFT backplane, to be the top gate insulator and top gate electrode of the defective BG TFT to obtain the defective dual-gate TFT. The mobility can be restored to 5.1 cm2 (V s)−1. Additional process steps are not required. Besides, this method is easily implemented and is fully compatible with TFT backplane fabrication process. The transfer curves, hysteresis characteristics, stabilities under constant voltage stress and constant current stress tests were measured to give evidences that the traps created by the plasma damage on the S/D regions indeed can affect electron transport. This trap-limited conduction can be improved by using the top gate. It was proven that the top gate was not for contributing an observably additional current. It was for inducing electrons to electrically passivate the plasma-induced defects near the back channel. Thus, the trapping/detrapping of the electrons transporting in the front channel can be reduced. The trap density near the Fermi level, hopping distance and hopping energy are 1.1 × 1018 cm−3 eV−1, 162 Å, and 52 meV for the BG TFT with plasma damage on the S/D regions.

Effects of constant voltage and constant current stress in PCBM:P3HT solar cells

The aim of this work is the investigation of forward and reverse bias stress effects, cell self-heating and annealing in roll coated organic solar cells with PCBM:P3HT active layer. In reverse bias stress cells show a constant degradation over time. In forward current stress cells alternate degradation and annealing phases, which are explained through the high power dissipation during the current stress, and the consequent self-heating. The high temperature is able to recover the cell performances at least until a critical temperature is reached. The degradation can be explained by the following mechanisms: the decrease of the net generation rate (due to formation of exciton quenching centres or the reduction of exciton separation rate); the formation of small leaky paths between anode and cathode, which reduces the total current extracted from the cell. The stress-induced damage can be recovered by thermal annealing at 120°C.

Ageing of InGaN-based LEDs: Effects on internal quantum efficiency and role of defects

This paper describes the degradation of InGaN-based LEDs submitted to constant current stress; based on combined electroluminescence, photoluminescence and deep-level transient spectroscopy we show that: (i) when submitted to constant current stress, LEDs can show a measurable decrease in the optical power, which is more prominent in the low current regime; (ii) the decrease in optical power is strongly correlated to the increase in the Shockley–Read–Hall recombination coefficient A, as estimated by differential lifetime measurements; (iii) stress induces the increase in the concentration of a trap level, with activation energy between 0.6 and 0.7eV, which is supposed to be located next to/within the active region. The results suggest that the optical degradation can be ascribed to the increase in non-radiative recombination, rather than to a decrease in carrier injection efficiency.

Capacity Fade Estimation in Electric Vehicle Li-Ion Batteries Using Artificial Neural Networks

In this paper, an artificial neural network (ANN) based approach is proposed to estimate the capacity fade in lithium-ion (Li-ion) batteries for electric vehicles (EVs). Besides its robustness, stability, and high accuracy, the proposed technique can significantly improve the state-of-charge (SOC) estimation accuracy over the lifespan of the battery, which leads to more reliable battery operation and prolonged lifetime. In addition, the proposed technique allows accurate prediction of the battery remaining service time. Two identical 3.6-V/16.5-Ah Li-ion battery cells were repeatedly cycled with constant current and dynamic stress test current profiles at room temperature, and their discharge capacities were recorded. The proposed technique shows that very accurate SOC estimation results can be obtained provided enough training data are used to train the ANN models. Model derivation and experimental verification are presented in this paper.

Degradation mechanisms and lifetime of state‐of‐the‐art green laser diodes

This paper presents a detailed analysis of the degradation kinetics and of the reliability of state‐of‐the‐art InGaN‐based green laser diodes (LDs), submitted to CW stress tests at different operating conditions. Results described in the following indicate that: (i) constant current stress induces an increase in threshold current (Ith), which is well correlated to a decrease in the sub‐threshold emission; (ii) the Ith increase has a power law dependence on stress time; (iii) the degradation rate is strongly dependent on the stress current level while it does not significantly depend on the optical field in the cavity; (iv) stress temperature acts as an accelerating factor for LDs degradation; the activation energy of the degradation process is equal to 258 meV; (v) pure thermal storage does not induce a significant degradation of device characteristics. Cathodoluminescence measurements were carried out to get more insight into the physical origin of the degradation process.

Control current stress technique for the investigation of gate dielectrics of MIS devices

AbstractIn this study, a modified technique of control current stress to investigation thin gate dielectric of MIS structures is proposed. This technique allows to monitor charge trapping in gate dielectric of MIS structures under high‐field and another stress situations (irradiation, plasma, hot carriers, etc.). The technique also may be used for testing thin gate dielectric defects. Unlike simple techniques, for example constant current stress and J‐ramp current stress, the proposed method uses a sequence of stress current and measuring current pulses. At the same time, the processes of charging and discharging of the MIS structure capacitance as well as the charge trapping in the gate dielectric are taken into account. Charging of MIS structure from inversion to accumulation modes or back way allows one to retrieve a low frequency capacitive‐voltage characteristic. Account charging capacitance of MIS structure and charge trapping in gate dielectric at injective mode lets considerably increase metrological characteristics of this technique and reduce inaccuracies. The models describing the change in the charge state of MIS structures, both in the charge capacity, and in the mode of injection of charge carriers were developed. Using these models let to choose optimal algorithm of current stress and increase measurement accuracy. (© 2015 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Operation methods of resistive random access memory

In this paper, different electrical measurement and operation methods of resistive random access memory (RRAM) have been summarized, including voltage sweeping mode (VSM), current sweeping mode (CSM), constant current stress (CCS), constant voltage stress (CVS), rectangular pulse mode (RPM), and triangle pulse mode (TPM). Meanwhile, the effects of these measurement methods on the forming, set, reset and read operation as well as endurance performance have been compared. Finally, their respective controllability of various resistive switching parameters have been summarized and analyzed.

Examination of the ambient effects on the stability of amorphous indium-gallium-zinc oxide thin film transistors using a laser-glass-sealing technology

The effect of an ambient atmosphere with a positive bias constant current stress (CCS) and a negative bias illumination stress (NBIS) on the stability of amorphous In-Ga-Zn-O thin film transistors (TFTs) is examined by utilizing a glass-hermetic-sealant with a moisture permeability of less than 10−6 g/m2 · day. In the CCS test, the threshold voltage shift (ΔVth) was remarkably suppressed in the glass-sealed TFTs. The unsealed and resin-sealed TFTs exhibited large ΔVth values. During the NBIS tests, the glass-sealed TFTs had almost the same negative ΔVth as the unsealed and resin sealed TFTs. Among the different TFTs, no significant differences were observed in the threshold voltage, the subthreshold swing and the saturation mobility as a function of the photon energy. It is concluded that ambient molecules were the primary origin of the instability of the ΔVth, induced by a CCS, but they were not related to the NBIS instability. The major role of the effective passivation layers in the NBIS test was not to simply block out the ambient effects, but to reduce the extra density of states at/near the surface of the back channel.

Conduction instability of amorphous InGaZnO thin-film transistors under constant drain current stress

Conduction characteristics of amorphous InGaZnO thin-film transistors were investigated by applying constant drain current with gate bias (VGS) modulation. Constant drain current in the off-current (Ioff) level from the transfer characteristic was applied to the drain electrode and the measured drain voltage with the gate bias sweep. The normalized channel conductance (Gd) characteristics were extracted from transfer characteristics and the gate bias modulated drain voltage characteristics with constant drain current stress were compared with the characteristics. The drain voltage induced by the constant drain current stress showed simultaneous transition from off-state with generation current dominant region with increasing drain bias (VDS) to the turn-on state. The high electric field at the drain electrode edge was observed at the threshold voltage (VTH), which can affect the instability characteristics of TFTs.