Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

Abstract

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (tBD) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the tBD values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO2 was observed between 27 and 225 °C.