A study of trap-limited conduction influenced by plasma damage on the source/drain regions of amorphous InGaZnO TFTs

Abstract

This study investigated electrical characteristics and stability variations of amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) with plasma damage on their source/drain (S/D) regions. The influence of the plasma damage on the TFT performance is absent as the channel length is 36–100 μm. When the channel length is decreased to 3–5 μm, the mobility () of the bottom gate TFT (BG TFT) with plasma damage is significantly degraded to 0.6 cm2 (V s)−1, which is much lower than 4.3 cm2 (V s)−1 of a damage-free BG TFT. We utilized the TFT passivation layer and the indium tin oxide (ITO), which was used as the pixel electrode material in the TFT backplane, to be the top gate insulator and top gate electrode of the defective BG TFT to obtain the defective dual-gate TFT. The mobility can be restored to 5.1 cm2 (V s)−1. Additional process steps are not required. Besides, this method is easily implemented and is fully compatible with TFT backplane fabrication process. The transfer curves, hysteresis characteristics, stabilities under constant voltage stress and constant current stress tests were measured to give evidences that the traps created by the plasma damage on the S/D regions indeed can affect electron transport. This trap-limited conduction can be improved by using the top gate. It was proven that the top gate was not for contributing an observably additional current. It was for inducing electrons to electrically passivate the plasma-induced defects near the back channel. Thus, the trapping/detrapping of the electrons transporting in the front channel can be reduced. The trap density near the Fermi level, hopping distance and hopping energy are 1.1 × 1018 cm−3 eV−1, 162 Å, and 52 meV for the BG TFT with plasma damage on the S/D regions.