Constant Capacitance Deep Level Transient Spectroscopy Research Articles

Effective Suppression of Amorphous Ga2O and Related Deep Levels on the GaN Surface by High-Temperature Remote Plasma Pretreatments in GaN-Based Metal-Insulator-Semiconductor Electronic Devices.

Gallium nitride (GaN) has been considered one of the most promising materials for the next-generation power and radio-frequency electronic devices, as they can operate at higher voltage, higher frequency, and higher temperature, compared with their silicon (Si) counterparts. However, the fresh GaN surface is susceptible to the natural oxidation composed of Ga2O3, Ga2O, and other intermediate oxidation states. Moreover, the oxidized GaN surface no longer features the distinct atomic step-terrace morphology, resulting in a degraded interface when gate or passivation dielectrics are deposited without appropriate pretreatment. It is responsible for the degraded performance of GaN-based devices such as current collapse and threshold voltage instability. In this study, the proposed high-temperature (500 °C) remote plasma pretreatments (RPPs) can play a significant role in addressing the issue of the deteriorated GaN surface exposed to air. Atomic step-terrace morphology was recovered after 500 °C-RPP due to the removal of oxides and suboxides. First-principles calculations verified that Ga2O at the GaN surface leads to interface states at ∼2.9 eV (EC-E ∼ 0.4 eV) in the bandgap, which is consistent with the increase of interface states at the EC-E range of 0.4-0.9 eV measured through constant-capacitance deep-level transient spectroscopy. Meanwhile, deep interface states and surface-related current collapse are well suppressed in GaN metal-insulator-semiconductor devices. These improved properties by 500 °C-RPP are generalizable to a broader range, including pre-gate and pre-passivation treatment, of which a decent surface/interface is desirable for high-performance GaN-based devices.

Effective suppression of deep interface states and dielectric trapping in SiNx/GaN metal-insulator-semiconductor structures by a SiOxNy interfacial layer grown by plasma-enhanced atomic layer deposition

A 3 nm-thick SiOxNy grown by plasma-enhanced atomic layer deposition (PEALD) at 500 °C is utilized as the interfacial layer to suppress the deep interface states and dielectric trapping in SiNx/GaN metal-insulator-semiconductor (MIS) structures. It is capable of protecting the GaN surface from decomposing during the growth of SiNx dielectric by low-pressure chemical vapor deposition (LPCVD) at a relatively high temperature of 780 °C. The SiNx/GaN interface with the PEALD-SiOxNy interfacial layer features a sharp interface, a remarkably reduced threshold voltage hysteresis (ΔVTH) as well as suppressed interface state density. The conduction band offset (ΔEC) between the LPCVD-SiNx dielectric and GaN increases from 2.67 to 3.77 eV by the PEALD-SiOxNy interfacial layer. It is verified by isothermal capture transient as well as constant-capacitance deep-level transient spectroscopy (CC-DLTS) measurements that the electron-trapping by the bulk states of EC-ET ∼ 1.1 eV in the LPCVD-SiNx dielectric and the deep interface states, can be effectively blocked by the PEALD-SiOxNy interfacial layer at high gate bias. The LPCVD-SiNx/ PEALD-SiOxNy bilayer could be a compelling gate dielectric for III-nitride MIS high-electron-mobility transistors (HEMTs).

Well-suppressed interface states and improved transport properties of AlGaN/GaN MIS-HEMTs with PEALD SiN gate dielectric

SiN deposited by plasma-enhanced atomic layer deposition (PEALD) is investigated as gate dielectric layer for GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The X-ray photoelectron spectroscopy (XPS) confirms low oxygen content in SiN-layer and the interface of SiN/(Al)GaN. The fabricated MIS-HEMTs exhibit significant reduction in gate leakage current (two or three orders of magnitude) and improvement in drain current (ID) characteristics, compared with the controlled HEMTs. A remarkable small threshold voltage (VTH) hysteresis (0.12 ± 0.05 V) and an enhanced 2DEG channel mobility are also achieved for PEALD SiN/(Al)GaN MIS-HEMTs. Simultaneously, a distribution of the interface states is quantitatively described by constant-capacitance deep-level transient spectroscopy (CC-DLTS), displaying a low density of 1.6 × 1013 cm−2 eV−1 at level depth of 0.03 eV and below 2.1 × 1012 cm−2 eV−1 at deep level depth of EC - ET > 0.4 eV. The suppressed interface traps density results in an improved performance for MIS-HEMTs. The dependence of the characteristics of MIS-HEMTs on SiN thickness (tSiN) was also studied in detail.

Suppression of interface states between nitride-based gate dielectrics and ultrathin-barrier AlGaN/GaN heterostructure with in situ remote plasma pretreatments

A silicon nitride (SiNx) film deposited at 500 °C by plasma-enhanced atomic layer deposition (PEALD) is employed as the gate dielectric for GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). An interface enhancement technology featuring in situ low-damage NH3/N2 remote plasma pretreatments (RPPs) is developed prior to the SiNx gate dielectric deposition, which contributes to an improved surface morphology while remarkably suppressed interface oxides. It is revealed by constant-capacitance deep-level transient spectroscopy that both shallow and deep states at the PEALD-SiNx/III-nitride interface are reduced by about one order of magnitude by the RPP. The in situ RPP and PEALD-SiNx gate dielectric process are implemented into fabrication of enhancement-mode MIS-HEMTs on an ultrathin-barrier AlGaN/GaN heterostructure technology platform. The fabricated MIS-HEMTs deliver an improved threshold stability and maximum output current as compared with devices without the RPP.

Capture and emission mechanisms of defect states at interface between nitride semiconductor and gate oxides in GaN-based metal-oxide-semiconductor power transistors

A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs.

Trap Characterization of ALD Al2O3/4H-SiC Metal-Oxide-Semiconductor Interfaces

4H-Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) are enabling high-efficiency power switching applications under high-temperature, and harsh environment conditions because of SiC’s superior physical properties. However, 4H-SiC MOSFETs have a much lower channel conductance due to the trapping of electrons by a high-density of near-interface traps (NITs) at the SiO2/4H-SiC interface [1,2]. These states are spatially located within ~1 nm from the interface and energetically positioned near the conduction band edge of 4H-SiC. Among the many approaches to solve this issue, using atomic layer deposition (ALD) of high k-dielectrics such as Al2O3 is promising. It has been reported that appropriate surface termination of 4H-SiC prior to ALD with hydrogen [3,4] or SiO [5,6] results in improved properties of Al2O3/4H-SiC MOS devices. The SiO termination refers to the insertion of an ultra-thin (~0.7 nm) silicon oxide layer between Al2O3 and 4H-SiC that results in effective channel mobility greater than 250 cm2Vs-1[5, 6]; significantly higher than that obtained by using standard nitrided (NO annealed) [7] SiO2 as the gate dielectric. In this work, we studied the above two surface termination approaches for ALD Al2O3 using electrical characterization and compared to typical thermally grown SiO2. To this end, Si-face n-type 4H-SiC MOS capacitors were fabricated and characterized using the simultaneous high-low frequency capacitance-voltage (CV), current-voltage (IV) and constant capacitance deep level transient spectroscopy (CCDLTS). For H- termination, prior to ALD, samples were etched in H2 at 1600 ◦C followed by annealing in H2 at 1000 ◦C [3, 4]. Following this, ALD was performed at 200 °C using Trimethylaluminum (TMA, Al(CH3)3) as the precursor to deposit ~50 nm of Al2O3. Electrical measurements were carried out after patterning and deposition of Au/Ti gates. In these samples, the interface state density (Dit ~3x1011 cm-2eV-1) near the conduction band edge was comparable to nitrided SiO2 as shown in Fig. 1. In addition, the CCDLTS showed that the typical ‘O1’ and ‘O2’ NITs[8] detected by CCDLTS at 4H-SiC/SiO2 interfaces, with emission activation energies of about 0.15±0.05 eV and 0.39±0.1 eV[4,8] below the 4H-SiC conduction band, were absent at these Al2O3/4H-SiC interfaces (Fig.2), which is extremely encouraging. In the second surface termination approach, ultra-thin (<1 nm) silicon oxide layers were grown thermally before Al2O3 deposition. Different oxidation conditions were employed varying the furnace temperature as 550 ◦C, 600 ◦C and 650 ◦C with 5 min oxidation time. Then, ~40 nm Al2O3 was deposited using the above ALD process and Al gate contacts were formed. Figure 3 shows the typical quasistatic CVs. It can be clearly observed that, with increasing oxidation temperature, the CV curves shift to the left indicating a reduction of negative charges at the interface, consistent with Dit reduction. However as shown in Fig.1, the simultaneous high-low CV reveals much higher Dit for these devices (~1x1013 cm-2eV-1 near the conduction band edge), comparable to typical unpassivated thermal oxides. Previous reports suggest that the ultra-thin oxide film thickness should be about ~0.7 nm to obtain low Dit and high channel mobility [5,6]. Our preliminary XPS analysis suggests that our film thickness is less than this critical value which might be the cause of the higher Dit here. Therefore, within our current results, we observe that surface H-termination prior to ALD of Al2O3 results in significantly lower Dit compared to SiO termination. Further studies with thicker SiO interlayers will be presented at the conference along with chemical bonding results from XPS analysis. Acknowledgments: This work was supported by the II-VI Foundation and US Army Research Lab. The authors thank Drs. Chunkun Jiao and Koushik Ramadoss from Purdue and Drs. Leonard C. Feldman and Ryan Thorpe from Rutgers University for sample fabrication and XPS analysis. [1] T. Kimoto, and J. A. Cooper, Fundamentals of Silicon Carbide Technology, John Wiley, 2014. [2] B. J. Baliga, Fundamentals of power semiconductor devices,1st edn., Springer, US, 2010. [3] T. Seyller, Appl. Phys. A. 85. 4. 371–385, Dec. 2006. [4] I. Jayawardhena, A. Jayawardena, C. Jiao, D. Morisette, and S. Dhar, Materials Science Forum, Proceedings of the 2018 ECSCRM (accepted 2019) [5] T. Hatayama, S. Hino, N. Miura, T. Oomori, and E. Tokumitsu, IEEE Trans. Electron Devices. 55. 8. 2041–2045. 2008. [6] J. Urresti, F. Arith, S. Olsen, N. Wright, and A. O’Neill, IEEE Trans. Electron Devices,66, 4, 1710–1716, Apr. 2019. [7] G. Y. Chung et al., Appl. Phys. Lett. 76. 13. 1713–1715, 2000. [8] A. F. Basile, J. Rozen, J. R. Williams, L. C. Feldman, and P. M. Mooney, J. Appl. Phys., 109, 6, 064514, Mar. 2011. Figure 1

Characterization of Near-Interface Traps at Dielectric/SiC Interfaces Using CCDLTS

Charge trapping at 4H-SiC/dielectric interfaces in 4H-SiC MOS capacitors has been investigated using constant capacitance deep level transient spectroscopy (CCDLTS). The experiments were focused on further understanding of the following aspects related to 4H-SiC/SiO2 interfaces: (i) Origin of near interface oxide traps (NITs), (ii) Effect of interfacial impurity/passivation methods and (iii) Characterization of near-interface oxide traps for different SiC wafer orientations. For the (0001) Si-face 4H-SiC/ SiO2 interface, two types of NITs are typically detected by CCDLTS, named ‘O1’ and ‘O2’ traps with emission activation energies of about 0.15±0.05 eV and 0.39±0.1 eV respectively below the 4H-SiC conduction band. Based on comparison with previous ab initio calculations, the physical identities of these defects have been suggested to be carbon dimers substituted for O dimers (‘O1’) and interstitial silicon atoms (‘O2’) in the near interfacial SiO2 respectively. In this work, it is shown for the first time that such traps are not observed for 4H-SiC/ Al2O3 interfaces, proving that these traps are inherent to the near-interfacial SiO2. In addition, the summary of CCDLTS results for Si-face with different interface trap passivation methods are included in this study. Finally, a comparison is presented for NO annealed (0001) Si-face, (11-20) a-face and (000-1) C-face interfaces that highlight the difference of CCDLTS signatures for the different crystal faces.

Improved SiO&lt;sub&gt;2&lt;/sub&gt;/ 4H-SiC Interface Defect Density Using Forming Gas Annealing

We investigated the influence of forming gas annealing (FGA) before and after oxide deposition on the SiO2/4H-SiC interface defect density (Dit). For MOS capacitors (MOSCAPs) that were processed using FGAs at temperatures above 1050°C, CV characterization revealed decreased flat band voltage shifts and stretch-out for different sweep directions and frequencies. Moreover, constant-capacitance deep level transient spectroscopy (CC-DLTS) was performed and showed Dit levels below 1012 cm-2eV-1 for post deposition FGA at 1200°C. Finally, lateral MOSFETs were fabricated to analyze the temperature-dependent threshold voltage (Vth) shift.

Characterization of SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Near-Interface Oxide Traps with Constant-Capacitance Deep-Level Transient Spectroscopy

A quantitative analysis method was proposed for near-interface oxide traps (NITs) at the SiC-MOS interface. Based on the tunneling capture model for electrons to the traps, characteristic parameters of NITs were clearly extracted from the pulse width dependence of the constant-capacitance deep-level transient spectroscopy (CC-DLTS) signal amplitude measured under isothermal conditions. To exclude capture processes other than direct tunneling, the pulse voltage was set to the flat-band voltage. The validity of the assumed model, in which the majority of the traps are localized at the interface and not distributed through the whole depth of the oxide, was demonstrated through comparison of the experimental results for two samples with different oxide thickness. The density of NITs at the MOS interface fabricated on 4H-SiC oxidized in a N2O atmosphere slowly decreases with the energy depth. The capture cross-section at the interface has no energy dependence, and has a value of 10-19 cm2.

Mechanism of phosphorus passivation of near-interface oxide traps in 4H–SiC MOS devices investigated by CCDLTS and DFT calculation

Interfacial charge trapping in 4H–SiC MOS capacitors with P doped SiO2 or phospho-silicate glass (PSG) as a gate dielectric has been investigated with temperature dependent capacitance–voltage measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements. The measurements indicate that P doping in the dielectric results in significant reduction of near-interface electron traps that have energy levels within 0.5 eV of the 4H–SiC conduction band edge. Extracted trap densities confirm that the phosphorus induced near-interface trap reduction is significantly more effective than interfacial nitridation, which is typically used for 4H–SiC MOSFET processing. The CCDLTS measurements reveal that the two broad near-interface trap peaks, named ‘O1’ and ‘O2’, with activation energies around 0.15 eV and 0.4 eV below the 4H–SiC conduction band that are typically observed in thermal oxides on 4H–SiC, are also present in PSG devices. Previous atomic scale ab initio calculations suggested these O1 and O2 traps to be carbon dimers substituted for oxygen dimers (CO=CO) and interstitial Si (Sii) in SiO2, respectively. Theoretical considerations in this work suggest that the presence of P in the near-interfacial region reduces the stability of the CO=CO defects and reduces the density of Sii defects through the network restructuring. Qualitative comparison of results in this work and reported work suggest that the O1 and O2 traps in SiO2/4H–SiC MOS system negatively impact channel mobility in 4H–SiC MOSFETs.

Effect of Wafer Orientation on Near-Interface Oxide Traps in 4H-SiC Metal-Oxide-Semiconductor Capacitors

4H-Silicon carbide is one of the enabling materials for modern high voltage and high temperature power electronic devices due to its attractive material properties. A significant drawback to SiC MOSFET performance is the low channel conductance due to trapping of carriers by the high-density of near-interface traps (NITs) at the SiO2/4H-SiC interface. These states are spatially located within ~1 nm from the interface and energetically positioned near the conduction band edge of 4H-SiC. Constant capacitance deep level transient spectroscopy (CCDLTS) technique is appropriate for analysis of such defects as it can differentiate between trap types and measure trapped charge emission rates. In this study, we examined SiO2-4HSiC interfaces formed on the polar (0001) Si- face (100% Si) and non-polar (11-20) a-face (50% Si, 50% C) oriented 4H-SiC wafers using CCDLTS. For the NO annealed Si-face interface, there are two main types of NITs detected by CCDLTS, labeled “O1” and “O2” traps by Basile et al. [1]. The physical identities of these defects have been suggested to be carbon dimers substituted for O dimers (CO=CO) and interstitial Silicon atoms in the near interfacial SiO2[2]. In this work, we observed both the O1 and O2 traps in the Si-face with activation energies of about 0.15±0.01 eV and 0.35±0.01 eV respectively, which are consistent with previous results[3]. The original result obtained in this study was that for the a-face; two new NITs (labeled A1 & A2) positioned very close to the O1 peak were observed but the O2 peak was absent. For this study, 4H-SiC MOS capacitors were fabricated on Si-face and a-face oriented wafers. The samples underwent dry oxidation followed by nitridation with NO annealing at 1175°C. After that, circular Al gates were evaporated as gate contact. The oxide thickness was ~62 nm and ~54 nm for Si-face and a-face respectively. CCDLTS was measured on capacitors keeping a constant capacitance in deep depletion in a temperature range of 77 K to 298 K changing pulse voltages and emission rates. Using the analysis method detailed in [1], the activation energies of the A1 and A2 peaks were found to be 0.15±0.01 eV and 0.19±0.01 eV respectively, which is in the same range as the O1 trap in the Si-face. The capture cross-sections for all traps detected was in the 10-16-10-14 cm2 range. Qualitatively, this result is similar to the results reported in [4], which shows that nitrided SiO2 formed on the (000-1) C-face (100% C terminated) also shows only one peak very similar to the O1 trap observed on the Si-face. This result points to the importance of interface structural differences due to different wafer orientation with respect to near-interface oxide traps. Acknowledgement: This work was supported by the II-VI foundation

Effect of Boro-Silicate Glass (BSG) Gate Dielectric with Antimony Surface Doping on Channel Transport of 4H-SiC Mosfets

In this work, we investigate the effect of Boro-silicate glass (BSG) gate dielectric in conjunction with Antimony (Sb) surface doped channels of lateral 4H-SiC MOSFETs. It has been reported that BSG gated 4H-SiC MOSFETs have a high channel mobility of ~100 cm2/V∙s for a wide range of surface transverse electric fields along with a large threshold voltage VT of ~5V in lightly doped p-epitaxial layers [1,2]. For vertical power MOSFETs with heavily doped p-wells, it is expected that BSG would cause an even further increase of VT (~10 V) which would be undesirable. Therefore in this work, our goal for combining the Sb surface doping process (demonstrated in our earlier works [3,4] and presented at ECSCRM 2014 [4]), with BSG gate dielectric was two-fold: (i) Tune VT to adequate value with high sub-threshold slope. (ii) Achieve high low-field channel mobility by Sb counter-doping while retaining the high-field mobility characteristics of BSG. The results from our experiments indicate that these goals were achieved. The 'Sb+BSG' process results in significant improvement of both low-field channel mobility to ~180cm2/V∙s (due to addition of Sb surface doping) and high-field channel mobility to ~90 cm2/V∙s (due to the BSG gate dielectric) along with a tuned threshold voltage of ~2V and a steeper sub-threshold slope. Lateral MOSFETs were fabricated on the Si-face of p-type 4H-SiC epitaxial layers doped at ~1x1016cm-3. Sb was implanted in the channel region with 80 keV at room temperature with dose of 2.5x1013cm-2, which results in a Gaussian profile with a depth of around 30nm below the surface of SiC. This was followed by post-implantation activation annealing at 1650°C using a graphitic carbon cap layer. Next, dry oxidation at 1150°C for 10 hours was performed followed by post-oxidation annealing using a planar diffusion source (Techneglas, GS-139) composed of boric oxide (B2O3) in a gas mixture of Ar (50sccm) and O2 (5sccm) at 950°C for 30 mins. Samples that received only boron annealing are referred to as 'BSG only' and samples underwent both Sb counter-doping and boron annealing are referred to as 'Sb+BSG'. Results for these samples are compared with standard NO-annealed devices in Table Ⅰ. The SIMS result in Fig. 1 shows B distributes throughout the oxide with a concentration of ~1x1022cm-3 and decreases as it reaches SiC. Threshold voltage and sub-threshold slope were characterized by Id-Vg measurement at room temperature and field-effect mobility was extracted from the transconductance of Id-Vg curve. Linear and log scale of Id-Vg curves in Fig. 2 and Fig. 3 demonstrate that 'Sb+BSG' tunes the threshold voltage to a more desirable value of ~2V along with a better sub-threshold slope than standard NO annealing. Fig. 4 shows a significant mobility improvement for 'Sb+BSG' at both high field due to the BSG passivation effect and low field due to the Sb counter-doping effect with a peak value of ~180cm2/V∙s compared to 'BSG only' with a peak mobility of ~140cm2/V∙s. In order to investigate the boron passivation effect on interface traps, C-V and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on the companion BSG capacitors. The interface trap density of 'NO' was determined to be ~2.5 times higher than that of 'BSG' for very shallow energy traps (<0.2 eV) from C-V measurements and ~1.5 times higher for the energy trap distributions centered at 0.15 eV and 0.39 eV by CCDLTS, as shown in Figs. 5 and 6. The mechanism of boron passivation has been suggested to be oxide stress relaxation by the reduction of required oxygen bonds due to the occupation of Si site by B [5]. In this presentation, further details of the nature of transport and mobility behavior in BSG gated channels will be presented as a function of temperature.

Effects of antimony (Sb) on electron trapping near SiO2/4H-SiC interfaces

To investigate the mechanism by which Sb at the SiO2/SiC interface improves the channel mobility of 4H-SiC MOSFETs, 1 MHz capacitance measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on Sb-implanted 4H-SiC MOS capacitors. The measurements reveal a significant concentration of Sb donors near the SiO2/SiC interface. Two Sb donor related CCDLTS peaks corresponding to shallow energy levels in SiC were observed close to the SiO2/SiC interface. Furthermore, CCDLTS measurements show that the same type of near-interface traps found in conventional dry oxide or NO-annealed capacitors are present in the Sb implanted samples. These are O1 traps, suggested to be carbon dimers substituted for O dimers in SiO2, and O2 traps, suggested to be interstitial Si in SiO2. However, electron trapping is reduced by a factor of ∼2 in Sb-implanted samples compared with samples with no Sb, primarily at energy levels within 0.2 eV of the SiC conduction band edge. This trap passivation effect is relatively small compared with the Sb-induced counter-doping effect on the MOSFET channel surface, which results in improved channel transport.

Electrical and structural characterizations of crystallized Al2O3/GaN interfaces formed by in situ metalorganic chemical vapor deposition

Al2O3 films were grown in situ by metalorganic chemical vapor deposition at 900 °C on GaN of both Ga- and N-face polarities. High-resolution transmission electron microscopy revealed that the Al2O3 films were crystalline and primarily γ-phase. The Al2O3/Ga-GaN and Al2O3/N-GaN interfaces were both atomically sharp, and the latter further exhibited a biatomic step feature. The corresponding current-voltage (J-V) characteristics were measured on a metal-Al2O3-semiconductor capacitor (MOSCAP) structure. The leakage current was very high when the Al2O3 thickness was comparable with the size of the crystalline defects, but was suppressed to the order of 1 × 10−8 A/cm2 with larger Al2O3 thicknesses. The interface states densities (Dit) were measured on the same MOSCAPs by using combined ultraviolet (UV)-assisted capacitance-voltage (C-V), constant capacitance deep level transient spectroscopy (CC-DLTS), and constant capacitance deep level optical spectroscopy (CC-DLOS) techniques. The average Dit measured by CC-DLTS and CC-DLOS were 6.6 × 1012 and 8.8 × 1012 cm−2 eV−1 for Al2O3/Ga-GaN and 8.6 × 1012 and 8.6 × 1012 cm−2 eV−1 for Al2O3/N-GaN, respectively. The possible origins of the positive (negative) polarization compensation charges in Al2O3/Ga-GaN (Al2O3/N-GaN), including the filling of interface states and the existence of structure defects and impurities in the Al2O3 layer, were discussed in accordance with the experimental results and relevant studies in the literature.

Deep-Level-Transient Spectroscopy Characterization of Mobility-Limiting Traps in SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Interfaces on C-Face 4H-SiC

Constant-capacitance deep-level-transient spectroscopy (CCDLTS) characterization of traps (or states) in SiO2/SiC interfaces on the C-face was carried out to clarify the cause of low-channel mobility of SiC MOSFETs. CCDLTS measurements showed that the interface-state density (Dit) near the conduction band of SiO2/SiC interfaces fabricated using N2O oxidation was much higher than that of SiO2/SiC interfaces fabricated using wet oxidation. The high density of interface states near the conduction band is likely to be the main cause of the low mobility of MOSFETs fabricated using N2O oxidation.

Electron Trapping in 4H-SiC MOS Capacitors Fabricated by Sodium-Enhanced Oxidation

The electrical properties of the SiO2/SiC interface fabricated by sodium-enhanced oxidation (SEO) of n-type 4H-SiC were studied by temperature-dependent C-V and constant-capacitance deep level transient spectroscopy (CCDLTS). With the exception of near-interface traps in the SiC epi-layer, which are not present in the SEO samples, the trap species observed in SEO capacitors are the same as those observed in both standard-oxidized and NO-annealed MOS capacitors. Total electron trapping in accumulation is comparable in SEO and NO-annealed capacitors; however, the traps in SEO capacitors are located at the interface whereas tunneling into oxide traps is observed in NO-annealed samples. A series of bias-temperature stress tests show that electron trapping is essentially unchanged when mobile sodium ions are moved toward the interface. The improved mobility attained by this process compared to NO annealing may be due to the absence of near-interface SiC traps in SEO samples.

Modeling of high-frequency capacitance-voltage characteristics to quantify trap distributions near SiO2/SiC interfaces

A procedure to calculate capacitance-voltage (C-V) characteristics from numerical solutions of the Poisson equation for metal-oxide-semiconductor (MOS) capacitors with traps located both at the oxide/semiconductor interface and in the semiconductor is presented. This method is tested for the simple case of a uniform distribution of a single acceptor or donor level in the semiconductor, for which an approximate analytical solution was derived by analogy with the results obtained for a Schottky diode within the depletion approximation. This method is then applied to model the high-frequency C-V curves of n-type 4H- and 6H-SiC MOS capacitors, which show a kink at depletion bias voltages that broadens with decreasing temperature below 150 K. This feature of the high-frequency capacitance occurs at the same temperature and voltage range as a signal detected by constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements and attributed to SiC traps. When only interface traps are considered, the trap energy distribution that is required to reproduce the kink in the C-V curves is not consistent with the trap energy distribution determined from CCDLTS measurements. Numerical simulations show that traps in the SiC epi-layer near the SiO2/SiC interface as well as interface traps with energies close to the SiC conduction band are necessary to explain both the CCDLTS measurement results and the temperature dependence of C–V curves.

Electron trapping in 4H-SiC MOS capacitors fabricated by pre-oxidation nitrogen implantation

Incorporation of nitrogen (N) atoms by ion implantation prior to oxidation of SiO2/4H-SiC interfaces has been investigated by capacitance-voltage (C-V) characteristics and constant capacitance deep-level-transient spectroscopy (CCDLTS) measurements. The shift of the C-V curves to negative voltages can be explained by the partial activation of implanted N atoms during oxidation. The maximum amplitude of the CCDLTS spectra, proportional to the density of near-interface oxide traps, decreases with increasing N dose, but remains significantly larger than that of SiO2/SiC interfaces fabricated by post oxidation annealing in nitric oxide (NO). Intrinsic defects in the SiC epi-layer associated with implantation damage are also observed in N-implanted samples. In contrast, electron traps energetically close to the SiC conduction band, detected in NO annealed samples and presumably introduced during oxidation, are not observed in N-implanted samples. The improved transport characteristics of MOS transistors fabricated on N-implanted epi-layers compared to those fabricated by NO annealing is suggested to result from the effects of the greater N donor concentration and also possibly to the suppression of shallow electron traps in the SiC epilayer.

Effect of NO Annealing on 6H- and 4H-SiC MOS Interface States

The electrical properties of the SiC/SiO2 interface resulting from oxidation of the n-type 6H-SiC polytype were studied by hi-lo CV, temperature dependent CV and constant capacitance deep level transient spectroscopy (CCDLTS) techniques. Several trap species differing in energy and capture cross section were identified. A trap distribution at 0.5 eV below the 6H-SiC conduction band energy and a shallower density of states in both the 6H and 4H polytyes are passivated by post-oxidation NO annealing. However, other ultra-shallow and deeper defect distributions remain after nitridation. The latter may originate from semiconductor traps.

Near-interface Traps in n-type SiO2/SiC MOS Capacitors from Energy-resolved CCDLTS

AbstractSilicon Carbide (SiC) Metal-Oxide-Semiconductor (MOS) capacitors, having different nitridation times, were characterized by means of Constant Capacitance Deep Level Transient Spectroscopy (CCDLTS). Electron emission was investigated with respect to the temperature dependence of emission rates and the amplitude of the signal as a function of the filling voltage. The comparison between the emission activation energies of the dominant CCDLTS peaks and the filling voltages, led to the conclusion that the dominant trapping behavior originates in the Silicon-dioxide (SiO2) layer. Moreover, a model of electron capture via tunneling can explain the dependence of the CCDLTS signal on increasing filling voltage.