Concurrent Error Detection Technique Research Articles

Improving dependability with low power fault detection model for skinny-hash.

The increasing popularity and prevalence of Internet of Things (IoT) applications have led to the widespread use of IoT devices. These devices gather information from their environment and send it across a network. IoT devices are unreliable due to their susceptibility to defect that arise intentionally or spontaneously. IoT devices must be dependable and secure since they form an integral part of the network that connects millions of connected objects. IoT devices are secured by cryptographic algorithms, but their dependability is a major concern. Concurrent error detection (CED) techniques, sometimes referred to as fault detection techniques, are extensively employed to enhance the dependability of embedded devices. Two fault detection approaches are proposed to detect faults in cryptographic algorithms running on IoT devices. Recomputing with complemented operands (RECO) and Double modular redundancy with complemented operands (DMRC) is proposed. Generally, IoT applications deploy resource-constrained devices and cannot support high-level security techniques. Therefore, the mentioned fault detection technique is assimilated for the lightweight SKINNY block cipher. The resource-sharing concept is applied to the SKINNY block cipher to reduce area overhead caused by DMRC. The SKINNY-Hash function construct is described using Very Large-Scale Hardware Description Language (VHDL). Functional behaviour is tested using ModelSim SE-64. The proposed architecture is synthesised using the Genus synthesis tool by Cadence, and area-power reports are generated. The proposed work is compared with the other CED techniques in terms of area and power consumption, and the work proves to have less overhead.

Improved error detection performance of logic implication checking in FPGA circuits

Increased feature scaling to achieve high performance of miniaturized circuits has increased concerns related to their reliability as smaller circuits age faster. This means that more computational errors due to defects are expected in modern nanoscale circuits. Logic implication checking is a concurrent error detection technique that can detect a partial number of these errors at reduced hardware costs. However, implications-based error detection suffers from a low error coverage in FPGA-implemented circuits making it useless for any practical purposes. In this paper, we identify the reasons for a degraded performance of implication checking in FPGAs and propose multi-wire implications towards achieving better error detection probabilities (Pdetection). The addition of multi-wire implications boosts the number of candidate implications and contributes more valuable implications thereby increasing the average Pdetection achieved by almost 1.7 times at around 65.7% with only a 25% increase in the average area overhead for the given test circuits. Moreover, we show that the efficiency of implications in detecting errors not only varies from one circuit to another but that it also depends largely on the specific implementation of the circuit under test as supported through analytic analyses and comparisons between experimental results obtained from hardware fault injection of the implemented circuits and fault simulations on corresponding circuit netlists.

A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs

Soft errors are an important issue for SRAM-based Field Programmable Gate Arrays (FPGAs), since they result in permanent alterations of the mapped circuit when they affect their configuration memory. Concurrent Error Detection (CED) techniques, such as Dual Modular Redundancy (DMR), are usually employed to detect errors that affect the performance of the circuit. When trying to detect errors produced on the complex Fast Fourier Transform (FFT), the Parseval Sum of Squares (SoS) is a widely used technique. In this paper, we present a scheme to implement CED techniques for the complex FFT implemented in SRAM-based FPGAs. These techniques perform checks based on the relationships existing between one or more of the inputs and the outputs of the algorithm. Three examples of these techniques are provided to further clarify how to construct them. These techniques, along with DMR and SoS, have been tested through fault injection. An analysis on their error detection capabilities shows that they achieve high detection rates with much less resource usage than DMR and SoS. In addition, the number of false error detections for these techniques is lower than that of SoS, which leads to less unnecessary reconfigurations of the device.

A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection

Compared with application specific integrated circuits (ASICs), static random access memory (SRAM)-based field programmable gate arrays (FPGAs) respond differently to radiation due to the configuration memory vulnerability. In this brief, the differences between the permanent error model for SRAM-based FPGAs due to configuration memory single event upsets (SEUs), and the ASIC SEU error model are put into perspective for error detection schemes. In particular, a concurrent error detection (CED) technique for finite impulse response filters in ASICs is implemented and evaluated in an SRAM-based FPGA through fault injection emulation. This method is compared with a dual modular redundancy (DMR) scheme in order to obtain a common behavior. The analysis of experimental data indicates that the CED technique has less undetected errors than DMR. However, our exhaustive fault injection tests reveal that false positive detections are more likely to occur in CED, since the error detection branch uses more FPGA resources than the DMR comparator. This phenomenon, which is negligible in ASICs, implies a partial or complete unnecessary reconfiguration, so it should be considered in SRAM-based FPGAs.

Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection

As a prominent attack approach against the security modules of integrated circuits, fault injection attacks (FIA) are able to breach thecryptographic primitives by analyzing the intentionally induced computation errors by adversaries. Parity-based Concurrent Error Detection (CED) techniques are often deployed as a countermeasure, owing to their low-overhead. Advanced linear and non-linear randomized encodings can be employed for constructing varying CED schemes. In this paper, we first evaluate the detection capability of linear parity-protected ciphers implemented in commercial FPGA, using laser fault injection (LFI) technique. A single-bit linear parity scheme is shown to be ineffective for error detection, since the LFI can typically flip multiple bits that are close to each other. On the other hand, a linear randomized parity scheme, with multiple bits parity, shows higher detection rates. Further, we study existing (randomized) non-linear encoding-based CED. With practical fault distributions on PRESENT cipher, non-linear randomized codes are extensively tested against fault injection. Although, known to have better theoretical detection bounds, non-linear encodings do not provide much improvements over simple randomized linear codes.

Parity driven reconfigurable duplex system

This paper proposes a method improving the fault-coverage capabilities of (FPGA) designs. Faults are mostly (SEUs) in the configuration memory of SRAM-based (FPGA) and they can change the functionality of an implemented design. These changes may lead to crucial mistakes and cause damage to people and environment. The proposed method utilizes Concurrent Error Detection techniques and the basic architectures of actual modern (FPGA) – the Look-Up Table (LUT) with two outputs. The main part of the paper is the description of the proposed method (PWtf) based on a cascade – waterfall – of several waves of inner parity generating the final parity of outputs of the whole circuit. The proposed PWtf method utilizes the (mostly) unused output of a two-output LUT to cover any single possible routing or LUT fault with a small area overhead. The encapsulation of the proposed PWtf method into a Duplication with Comparison scheme is presented in the second part of the paper. This encapsulation allows us to create a system containing two independent copies of all parts able to detect and localize any single fault (like common Triple Modular Redundancy method). Experiments are performed on the standard set of IWLS2005 benchmarks in our simulator. The results demonstrate differences between our proposed method and a similar existing technique – Duplication with Comparison (DwC), and between the encapsulated PWtf method and TMR. The proposed method has a lower relative overhead and requires a lower number of inputs and outputs.

English

An Error Correction code with Parity check matrix is implemented which is other type of the One Step Majority Logic Decodable (OS-MLD) called as Orthogonal Latin Squares (OLS) codes. It is a concurrent error detection technique for OLS codes encoders and syndrome computation because of the fact that when ECCs are used, the encoder and decoder circuits can also suffer errors.These OLS codes are used to correct the memories and caches. This can be achieved due to their modularity such that the error correction capabilities can be easily adapted to the error rate or to the mode of the operation.OLS codes typically require more parity bits than other codes to correct the same number of errors. However, due to their modularity and the simple low delay decoding implementation these are widely used in Error Correction. All the errors that affect a single circuit node are detected by the parity prediction scheme. The area and latency values are monitored.

Fault Tolerant Techniques for Finite Field Multipliers

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

Fault-Duration And-Location Aware CED Technique With Runtime Adaptability

In response to the rising fault susceptibility of integrated circuits due to aggressive device scaling, a number of concurrent error detection (CED) techniques have been proposed. However, many of these CED techniques do not concern power. Even worse, these techniques are inefficient or even incapable of addressing the new challenges brought about by nanometer devices. In this paper, we propose a new register-transfer-level CED technique that comprehensively considers power efficiency and fault security. Its CED capability can be adjusted at runtime according to the actual need. The proposed high-level synthesis technique ensures that the generated datapath consumes minimal power for any fault scenario it has been turned to.

ERROR DETECTION SCHEMES FOR FINITE FIELD MULTIPLIERS

Finite field multipliers are widely used in the fie ld of cryptography for the purpose of scalar multip lication. The outputs of the finite field multipliers may con sist of errors due to certain natural radiations wh ich further leads to the failure of the cryptosystems. Here two Concurrent Error Detection (CED) schemes namely time redundancy and modular inversion based error detection schemes for finite field multiplier s are discussed. The CED techniques have been implemented for bit serial, digit serial and bit parallel Montgomery multipliers. The Simulation results are obtained using Modelsim10.0b, area and power analysis has been performed using Xilinx ISE 9.1i. The proposed modular inversion based CED scheme is found to be area and power efficient compared to ex isting time redundancy based CED scheme.

Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation

Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node.

Recomputing with Permuted Operands: A Concurrent Error Detection Approach

Naturally occurring and maliciously injected faults reduce the reliability of cryptographic hardware and may leak confidential information. We develop a concurrent error detection technique (CED) called recomputing with permuted operands (REPO). We show that it is cost effective in advanced encryption standard (AES) and a secure hash function Grøstl. We provide experimental results and formal proofs to show that REPO detects all single-bit and single-byte faults. Experimental results show that REPO achieves close to 100% fault coverage for multiple byte faults. The hardware and throughput overheads are compared with those of previously reported CED techniques on two Xilinx Virtex FPGAs. The hardware overhead is 12.4%-27.3%, and the throughput is 1.2-23 Gbps, depending on the AES architecture, FPGA family, and detection latency. The performance overhead ranges from 10% to 100% depending on the security level. Moreover, the proposed technique can be integrated into various block cipher modes of operation. We also discuss the limitation of REPO and its potential vulnerabilities.

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

This paper presents a new recovery scheme for dealing with short-to-long duration transient faults in combinational logic. The new scheme takes earlier into account results of concurrent error detection (CED) mechanisms, and then it is able to perform shorter recovery latencies than existing similar strategy. The proposed scheme also requires less memory resources to save input contexts of combinational logic blocks. In addition, this work also proposes a taxonomy of CED techniques. It allows pointing out which are the necessary recovery resources as well as identifying which are the types of CED mechanisms that can be used with the new recovery scheme of this paper. The effectiveness of the proposed scheme was evaluated through electrical-level simulations. For all short-to-long duration transient-fault injections, it was never slower than state-of-art similar strategy, and indeed its recovery latency was faster for 34 % of the simulated faulty scenarios.

Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms

In this paper, a novel low-complexity Concurrent Error Detection (CED) technique for Fast Fourier Transform-based convolution is proposed. The technique is based on checking the equivalence of the results of time and frequency domain calculations of the first sample of the circular convolution of the two convolution input blocks and of two consecutive output blocks. The approach provides low computational complexity since it re-uses the results of the convolution computation for CED checking. Hence, the number of extra calculations needed purely for CED is significantly reduced. When compared with a conventional Sum Of Squares – Dual Modular Redundancy technique, the proposal provides similar error coverage for isolated soft errors at significantly reduced computational complexity. For an input sequence consisting of complex numbers, the proposal reduces the number of real multiplications required for CED in adaptive and fixed filters by 60% and 45%, respectively. For input sequences consisting of real numbers, the reductions are 66% and 54%, respectively.

Very-low-complexity concurrent error detection for transform-based filters

A very-low-complexity concurrent error detection technique for filters implemented in the frequency domain using the fast Fourier transform and the overlap-add method is presented. The proposed approach checks the first or last sample of every output block by comparing it with the equivalent value calculated in the time domain. The check requires only one additional multiplication per output block. Thus, the computational complexity of the check is negligible. It is shown that the method is capable of detecting a significant percentage of errors.

Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks

Secure operation of cryptographic algorithms is critical to the success of secure transactions. Fault-based attacks that recover secret keys by deliberately introducing fault(s) in cipher implementations and analyzing the faulty outputs have been proven to be extremely powerful. Substitution Permutation Networks (SPN) and Feistel Networks (FN) are the two important classes of Symmetric Block Ciphers. Some SPN ciphers and all FN Ciphers satisfy the involution property. A function F is an involution if F(F(x)) = x. In this paper, we investigate tamper proofing techniques that use low cost involution-based time redundancy concurrent error detection (CED) schemes for involutional SPN and FN symmetric block ciphers. We incorporated this tamper proofing by design technique in a hardware implementation of the 128-bit ANUBIS SPN cipher (an involution variant of the Advanced Encryption Standard (AES)) and the 128-bit TwoFish FN cipher (an AES finalist). We performed fault simulation at both the algorithm and the gate level to show that the low-cost involution-based CED schemes, in addition to detecting all transient faults, can detect all single-bit permanent faults and > 99 percent of all multiple-bit permanent faults. Consequently, this low cost CED technique can protect the crypto device against Differential Fault Analysis (DFA) attacks.

Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design

In this paper, a time redundancy based Concurrent Error Detection (CED) technique targeting involutional functions is presented. A function F is an involution if F(F(x))=x. The proposed CED technique exploits the involution property and checks if x=F(F(x)). Unlike traditional time redundancy based CED methods, this technique can detect both permanent and transient faults.

Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique

This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED) technique. In REcomputing with Shifted Operands (RESO), operations (additions, subtractions, etc.) are carried out twice-once on the basic input and once on the shifted input. Results from these two operations are compared to detect an error. Although using RESO operators in RT-level designs is straightforward, it entails time and area overhead. In contrast, ARESO does not use specialized RESO operators. In ARESO, an algorithm is carried out twice-once on the basic input and once on the shifted input. Results from these two algorithm-level instantiations are compared to detect an error. By operating at the algorithm level, ARESO exploits RT-level scheduling, pipelining, operator chaining, and multicycling to incorporate user-specified error detection latencies. ARESO supports hardware versus performance versus error detection latency tradeoffs. The authors validated ARESO on practical design examples using the Synopsys Behavior Compiler (BC). An industry standard behavioral synthesis system.

Fault tolerance design in JPEG 2000 image compression system

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The new standard is based on wavelet technology and layered coding in order to provide a rich feature compressed image stream. The implementations of the JPEG 2000 codec are susceptible to computer-induced soft errors. One situation requiring fault tolerance is remote-sensing satellites, where high energy particles and radiation produce single event upsets corrupting the highly susceptible data compression operations. This paper develops fault tolerance error-detecting capabilities for the major subsystems that constitute a JPEG 2000 standard. The nature of the subsystem dictates the realistic fault model where some parts have numerical error impacts whereas others are properly modeled using bit-level variables. The critical operations of subunits such as discrete wavelet transform (DWT) and quantization are protected against numerical errors. Concurrent error detection techniques are applied to accommodate the data type and numerical operations in each processing unit. On the other hand, the embedded block coding with optimal truncation (EBCOT) system and the bitstream formation unit are protected against soft-error effects using binary decision variables and cyclic redundancy check (CRC) parity values, respectively. The techniques achieve excellent error-detecting capability at only a slight increase in complexity. The design strategies have been tested using Matlab programs and simulation results are presented.

Fault Secure Datapath Synthesis Using Hybrid Time and Hardware Redundancy

A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' behavioral compiler.