Abstract
Finite field multipliers are widely used in the fie ld of cryptography for the purpose of scalar multip lication. The outputs of the finite field multipliers may con sist of errors due to certain natural radiations wh ich further leads to the failure of the cryptosystems. Here two Concurrent Error Detection (CED) schemes namely time redundancy and modular inversion based error detection schemes for finite field multiplier s are discussed. The CED techniques have been implemented for bit serial, digit serial and bit parallel Montgomery multipliers. The Simulation results are obtained using Modelsim10.0b, area and power analysis has been performed using Xilinx ISE 9.1i. The proposed modular inversion based CED scheme is found to be area and power efficient compared to ex isting time redundancy based CED scheme.
Highlights
Secured data communication in the presence of third parties
Finite fields are used in a variety of applications including classical coding theory in linear block codes 2005; Biham and Shamir, 1997; Boneh et al, 1997).The Montgomery multiplication algorithm is used to enhance the scalar multiplication in Elliptic Curve Cryptography (ECC) (Montgomery, 1985)
The data flow for the Concurrent Error Detection (CED) scheme using modular inversion in the block diagram is explained in two steps as follows: During the first step the two inputs (A(x), B(x)) are multiplied using the Montgomery multiplication algorithms (Bit serial, Digit serial or Bit Parallel)
Summary
Secured data communication in the presence of third parties. ECC (Miller, 1998) is an approach to public key. Finite field multipliers use Montgomery multiplication algorithm to perform bit serial, digit serial and bit parallel multiplier operations (Ananyi et al, 2009; Koc and Acar, 1998; Fan and Dai, 2005; Hariri and Reyhani-Masoleh, 2008). The bit parallel systolic finite field multiplier over polynomial basis has been implemented for irreducible polynomial, all-one polynomial and irreducible trinomial (Sargunam et al, 2012a). The speed of bit parallel systolic finite field multiplier over polynomial basis has been improved using an unique technique (Sargunam et al, 2012b). The first step is performed by applying inputs A(x) and B(x) to the Montgomery Multiplier array and the result C(x) is converted by the *xm circuit to C’(x) and stored in latches
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