Fault-Duration And-Location Aware CED Technique With Runtime Adaptability

Abstract

In response to the rising fault susceptibility of integrated circuits due to aggressive device scaling, a number of concurrent error detection (CED) techniques have been proposed. However, many of these CED techniques do not concern power. Even worse, these techniques are inefficient or even incapable of addressing the new challenges brought about by nanometer devices. In this paper, we propose a new register-transfer-level CED technique that comprehensively considers power efficiency and fault security. Its CED capability can be adjusted at runtime according to the actual need. The proposed high-level synthesis technique ensures that the generated datapath consumes minimal power for any fault scenario it has been turned to.