Printed Circuit Board Components Research Articles

Nondestructive testing method for a new generation of electronics

The implementation of the Smart City system needs reliable and smoothly operating electronic equipment. The study is aimed at developing a nondestructive testing method for electronic equipment and its components. This method can be used to identify critical design defects of printed circuit boards (PCB) and to predict their service life, taking into account the nature of probable operating loads. The study uses an acoustic emission method to identify and localize critical design defects of printed circuit boards. Geometric dimensions of detected critical defects can be determined by the X-ray tomography method. Based on the results of the study, a method combining acoustic emission and X-ray tomography was developed for nondestructive testing of printed circuit boards. The stress-strain state of solder joints containing detected defects was analyzed. This paper gives an example of using the developed method for estimating the degree of damage to joints between PCB components and predicting the service life of the entire PCB.

Design techniques for a stable operation of cryogenic field-programmable gate arrays.

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Analysis of surface insulation resistance related failures in electronics by circuit simulation

PurposeThe purpose of this study is to show that the humidity levels for surface insulation resistance (SIR)-related failures are dependent on the type of activators used in no-clean flux systems and to demonstrate the possibility of simulating the effects of humidity and contamination on printed circuit board components and sensitive parts if typical SIR data connected to a particular climatic condition are available. This is shown on representative components and typical circuits.Design/methodology/approachA range of SIR values obtained on SIR patterns with 1,476 squares was used as input data for the circuit analysis. The SIR data were compared to the surface resistance values observable on a real device printed circuit board assembly. SIR issues at the component and circuit levels were analysed on the basis of parasitic circuit effects owing to the formation of a water layer as an electrical conduction medium.FindingsThis paper provides a summary of the effects of contamination with various weak organic acids representing the active components in no-clean solder flux residue, and demonstrates the effect of humidity and contamination on the possible malfunctions and errors in electronic circuits. The effect of contamination and humidity is expressed as drift from the nominal resistance values of the resistors, self-discharge of the capacitors and the errors in the circuits due to parasitic leakage currents (reduction of SIR).Practical/implicationsThe methodology of the analysis of the circuits using a range of empirical leakage resistance values combined with the knowledge of the humidity and contamination profile of the electronics can be used for the robust design of a device, which is also important for electronic products relying on low current consumption for long battery lifetime.Originality/valueExamples provide a basic link between the combined effect of humidity and contamination and the performance of electronic circuits. The methodology shown provides the possibility of addressing the climatic reliability of an electronic device at the early stage of device design by using typical SIR data representing the possible climate exposure.

Cross-guide Moreno directional coupler in empty substrate integrated waveguide

Substrate integrated waveguides (SIWs) combine the advantages of rectangular waveguides (low losses) and planar circuits (low cost and low profile). Empty substrate integrated waveguide (ESIW) has been proposed as a novel configuration in SIWs recently. This technology significantly reduces the losses of conventional SIW by removing its inner dielectric. The cross-guide directional coupler is a well-known low-profile design for having a broadband waveguide coupler. In this paper a cross-guide coupler with ESIW technique is proposed. In such a manner, the device can be integrated with microwave circuits and other printed circuit board components. It is the first time that a cross-guide coupler is implemented in ESIW technology. The designed, fabricated, and measured device presents good results as a matter of insertion loss of 1 dB (including transitions), reflection under 20 dB, coupling between 19.5 and 21.5 dB, and directivity higher than 15 dB over targeted frequency range from 12.4 GHz to 18 GHz. The coupler implemented in ESIW improves the directivity when compared to similar solutions in other empty substrate integrated waveguide solutions.

Characterisation of Printed Circuit Boards of Mobile Phones Discarded in Brazil

The characterisation of printed circuit boards (PCB) removed from discarded mobile phones in Brazil and an inventory of data of the components in PCB were accomplished in this paper. Data of chemical composition of PCB were obtained from the physicochemical characterisation of their components through the analysis of granulometry, scanning electron microscopy with energy dispersive x-ray detector (SEM/EDS), infrared spectroscopy (FT-IR) and inductively coupled plasma optical emission spectrometry (ICP-OES). The analysis allowed a broad view and a highlight for the wide variety of elements and heterogeneity of the material. It can be also highlighted the high amount of copper, lead and other high-value metals in the PCB. This study is relevant for the development of new recycling technologies, once this material has been discarded incorrectly in Brazil. Based on the percentage of mobile phones recycled and disposed in Brazil, it is possible to quantify financial loss resulting from incorrect disposal.

Plant-Based Completely Biodegradable Printed Circuit Boards

Completely biodegradable printed circuit boards (PCBs) have been developed using biocomposites made from natural cellulose fibers extracted from banana stems and wheat gluten, which are normally considered as agricultural wastes or coproducts. PCBs were fabricated using these composites with properties suitable for electronic applications. The biocomposites are free of chemicals, and an environmentally benign approach was adopted to fabricate the PCBs. Conventional PCBs are critical components in electronics and are currently made using fire resistant plastics (FRPs). FRPs are typically made using glass fibers and epoxy, which are nonbiodegradable when disposed in the environment. Several attempts have been made to develop environmentally friendly PCBs and other electronic components. Although dissolvable electronics and foldable PCBs have been reported, so far, there are no 100% biodegradable PCBs. The dielectric constant for banana fiber/wheat gluten composite varied between 2–36, which is in the range of dielectric materials used for PCB and other electronic components. A significant amount of heat (up to 45 °C) was dissipated through the biocomposite preventing overheating and thus reducing risk of fires. PCBs did not show any deterioration in performance even after exposure to high humidity (90%) or high temperature (100 °C). LED connected to the PCB was able to glow without any interruption. Natural fibers and protein-based PCBs may provide an alternative to the synthetic polymer-based electronic components and help us to reduce the environmental burden due to the disposal of electronic waste (e-waste).

Optimization of printed circuit board component placement using an efficient hybrid genetic algorithm

The hardware restrictions of surface mount placement machines, such as height, pick and place restrictions, and simultaneous pickup are often in printed circuit board (PCB)-related studies. This study proposes an efficient hybrid genetic algorithm (HGA) for solving the nozzle assignment problem and the component pick and place sequence problem. First, the proposed method obtains the sequence of the automatic nozzle changer (ANC) with the maximum number of simultaneous pickups and the minimum number of picks as the solution of the nozzle setup problem. Then, the proposed method uses the nearest neighbor search (NNS), 2-optimization, and a genetic algorithm (GA) with the known ANC sequences to obtain the PCB assembly time with the optimal component pick and place sequence. Experiments are conducted on the PCB of the EVEST EM-780 surface mount placement machine. Results show that the proposed HGA gives the lowest total number of picks, the shortest total head movement distance, and the minimum total PCB assembly time compared to those of other methods.

Heavy-Weight Component First Placement Algorithm for Minimizing Assembly Time of Printed Circuit Board Component Placement Machine

This paper deals with the PCB assembly time minimization problem that the PAP (pick-andplacement) machine pickup the -weighted group of -components, loading, and place into the PCB placement location. This problem considers the rotational turret velocity according to component weight group and moving velocity of distance in two component placement locations in PCB. This paper suggest heavy-weight component group first pick-and-place strategy that the feeder sequence fit to the placement location Hamiltonean cycle sequence. This algorithm applies the quadratic assignment problem (QAP) that considers feeder sequence and location sequence, and the linear assignment problem (LAP) that considers only feeder sequence. The proposed algorithm shorten the assembly time than iATMA for QAP, and same result as iATMA that shorten the assembly time than ATMA. ▸

Embedding components in voltage converter PCB for size reduction and heat management

Purpose – The purpose of this paper was to show physical limitation of embedding standard packaging components into printed circuit board (PCB) which is more reasonable technology for small series productions which is popular in industrial products. Embedding electronic components inside a PCB FR-4 substrate leads to significant size reduction and better heat management. Embedded chip technology is already known in many consumer electronics applications, but it is focused on high volumes and required to order components ready to be embedded. Design/methodology/approach – Highly integrated DC/DC converter with standard-package electronic parts (passive and active) was embedded inside a PCB structure. The design and the manufacturing process was based on standard PCB FR-4 technology. Sandwich solution was used to integrate all layers together; one of the main investigations was to focus on how to fill space around components to keep internal stresses on very low level. Findings – There were few considerations during choosing the right concept. The first, which occurred during the first producing round, was the distance between thick copper and inner layer. The second one was the way how to fill space between mounted components on inner layer and isolation laminate. A few trials took place and it is decided that it is impossible to fill this space with resin from prepregs; therefore, a casting compound was used. Originality/value – Design and manufacturing process which brings 37 per cent of size reduction of complete DC/DC voltage converter PCB with 28.5 W output power comparing to a reference design with standard surface mounted devices (SMD) and copper layout implementation has been achieved during research project.

Thermal fluid-structure interaction of PCB configurations during the wave soldering process

Purpose – This paper aims to investigate the thermal fluid–structure interactions (FSIs) of printed circuit boards (PCBs) at different component configurations during the wave soldering process and experimental validation. Design/methodology/approach – The thermally induced displacement and stress on the PCB and its components are the foci of this study. Finite volume solver FLUENT and finite element solver ABAQUS, coupled with a mesh-based parallel code coupling interface, were utilized to perform the analysis. A sound card PCB (138 × 85 × 1.5 mm3), consisting of a transistor, diode, capacitor, connector and integrated circuit package, was built and meshed by using computational fluid dynamics pre-processing software. The volume of fluid technique with the second-order upwind scheme was applied to track the molten solder. C language was utilized to write the user-defined functions of the thermal profile. The structural solver analyzed the temperature distribution, displacement and stress of the PCB and its components. The predicted temperature was validated by the experimental results. Findings – Different PCB component configurations resulted in different temperature distributions, thermally induced stresses and displacements to the PCB and its components. Results show that PCB component configurations significantly influence the PCB and yield unfavorable deformation and stress. Practical implications – This study provides PCB designers with a profound understanding of the thermal FSI phenomenon of the process control during wave soldering in the microelectronics industry. Originality/value – This study provides useful guidelines and references by extending the understanding on the thermal FSI behavior of molten solder for PCBs. This study also explores the behaviors and influences of PCB components at different configurations during the wave soldering process.

Combining diagonal connection and cancellation turn in electromagnetic interference filtering

In this study, a new printed circuit board (PCB) implementation of the diagonal connection is proposed. The two capacitors that are connected diagonally are laid out as close as possible and in such a way that their currents have opposite directions. The new layout combines the benefits of the so-called 'cancellation turn' with the benefits of the diagonal connection, without the need for additional PCB space and components. The experimental results show that the self-resonant frequency of the diagonally connected capacitors increased by 32%. Additionally, the coupling between the diagonally connected capacitors and a capacitor on the other side of the filter was reduced by 20-25 dB.

Non-uniform PCB traces with prescribed frequency bands for improved crosstalk immunity

In this work, a new design approach for realizing printed circuit board (PCB) trace configuration with continuous impedance perturbation to reduce crosstalk in PCB interconnects is investigated. The purpose is to reduce far-end crosstalk without incorporating additional PCB components in order to modify the reactive couplings between the adjacent traces, however at the expense of the available frequency band. This is achieved by replacing a uniform victim trace on a PCB with a continuously varying-impedance trace that exhibits a lowpass filter frequency characteristic. A simplified design approach of the proposed trace impedance profile which is governed by a truncated fourier series is presented. The proposed trace shows better crosstalk reduction results compared to conventional intervening guard trace schemes. Several configurations were designed, implemented, and tested to demonstrate the advantages of the underlying principle.

Crosstalk Reduction Using Defective Ground Plane Structures In RF Printed Circuit Boards

A new crosstalk reduction technique is proposed, which utilizes defective ground plane structures. With some basic defective ground plane structures, near end crosstalk (NEXT) and far end crosstalk (FEXT) of the coupled lines are reduced, without significant change in signal transmission property. As per the 3X thumb rule, the spacing between two traces must be three times that of the trace width, in order to avoid crosstalk. Without using additional Printed Circuit Board components in the design, a new method is proposed to reduce the crosstalk with the spacing of 0.5 mm and the line width chosen for 50 Ω characteristic impedance. The method proposed has been validated by fabrication and measurements. Both time domain and frequency domain responses are analyzed. Due to the narrow band property of these defective ground structures, the usable bandwidth is narrow. In order to achieve wide usable bandwidth, multiple defective ground structures are used.

Defect Detection of SMT Electronic Modules

To automatically detect SMT (surface mount technology) electronic modules, algorithms are investigated for geometry and shape features, module matching and detection in PCB (printed-circuit board) components. First, geometry and shape features of SMT electronic modules are presented. Then matching technology and process for SMT electronic modules are studied through optimization searching algorithms, such as similarity based detection and pyramid algorithms. Based on the analysis of major defects, algorithms for detecting major defects in SMT electronic modules are investigated. Finally, the crucial factors affecting inspection precision and speed, i.e., components contour, searching range and minimum similarity, are analyzed. The experimental results show the detection time for Circuit Boards without defect is 0.82s, and for those with one component absent 0.89s, yet for multiple components absent 10.68s. Therefore, it can satisfy the requirements of high reliability, stability, precision, inspection speed and anti-interference for defect detection in SMT electronic module of Circuit Boards.

Evaluation of Inherent Uncertainties of the Homogeneous Effective Thermal Conductivity Approach in Modeling of Printed Circuit Boards for Space Applications

Electronic components are normally assembled to printed circuit boards (PCBs). Such components generate heat in operation which must be conducted away efficiently from the small mounting areas to frames where the PCB is fixed. The temperature of the component depends on heat dissipation rate, technology and parameters of mounting, component placement and finally effective thermal conductivity (keff) of the board. The temperature of some components may reach significant magnitudes over 100°C while the PCB frame is kept at near-ambient temperature. The reliability of electronic components is directly related to operating temperature; so the thermal project should be able to provide a correct temperature prediction of all PCB components under the hottest operational condition. In space applications, the main way to spread and reject heat of electronic equipment is by thermal conduction once there is no air available to apply convection-based cooling techniques. The PCB keff is an important parameter for the electronics thermal analysis when the PCB is modeled as a simplified homogeneous board with a unique thermal conductivity. In this paper, an intrinsic uncertainty of such approach is firstly reveled and its magnitude is evaluated for a real space use PCB. The simulation uses SINDA/FLUINT Thermal Desktop and aims to determine the keff of the PCB by comparison between a detailed multi-layered anisotropic model and an equivalent homogeneous single-layer model. The model was validated using available data for two-layered FR4-copper PCB. Multiple simulations are performed with different dissipating component position and mounting area.

A single machine carryover sequence-dependent group scheduling in PCB manufacturing

This paper considers the problem of minimizing the makespan on a single machine with carryover sequence-dependent setup times. A similar problem with multi-machine flow shop usually arises in the assembly of printed circuit boards (PCBs). This research investigates the possibility of processing all components of PCBs using just one machine. By doing so the operational costs of having multi-machines can be reduced, and as a result, finding an optimal solution might be more plausible. The objective is to minimize the maximum completion time of all board groups, commonly known as makespan. The operational constraints are such that all board types within a board group must be completely kitted, as it is traditionally performed by kitting staff, before that board group begins its assembly operation. We introduce the external setup (kitting) time and require that it be performed solely by the machine operator during the run time of the current board group, and thereby completely eliminating the need for kitting staff. The carryover sequence-dependent setup time, namely the internal (machine) setup time, is realized when a new board group is ready for assembly operation and is dependent on all of the previously scheduled board groups and their sequences. To the best of our knowledge, this is the first time the external and internal setup times are integrated in PCB group scheduling research. We develop a branch-and-bound algorithm and a lower-bounding structure. The lower bound consists of two approaches, which enable the algorithm to simultaneously reduce performing unnecessary exploration. In order to test the efficiency of the algorithm, several problem instances with different board groups have been used. The algorithm developed requires a significantly large computation time to optimally solve very large problems. Thus to speak for the efficiency in terms of solving comparable large industry-size problems, we evaluate the deviation of the algorithm from the lower bound which turns out to be very small, with an average of only 6%, in all of the problem instances considered.

Chaotic species based particle swarm optimization algorithms and its application in PCB components detection

An improved particle swarm optimizer using the notion of chaos and species is proposed for solving a template matching problem which is formulated as a multimodal optimization problem. Template matching is one of the image comparison techniques. This technique is widely applied to determine the existence, location and alignment of a component within a captured image in the printed circuit board (PCB) industry where 100% quality assurance is always required. In this research, an efficient auto detection method using a multiple templates matching technique for PCB components detection is described. The new approach using chaotic species based particle swarm optimization (SPSO) is applied to the multi-template matching (MTM) process. To test its performance, the proposed Chaotic SPSO based MTM algorithm is compared with other approaches by using real captured PCB images. The Chaotic SPSO based MTM method is proven to be superior to other methods in both efficiency and effectiveness.

Automated extraction of PCB components based on specularity using layered illumination

This paper investigates the methodologies for locating and identifying components on a printed circuit board (PCB) used for surface mount device inspection. It's the foundation of other inspections...

Far-end crosstalk reduction in PCB interconnects using stepped impedance elements and open-circuited stubs

In this work, new trace configurations using stepped impedance elements and open-circuited stubs to reduce far-end crosstalk in printed circuit board (PCB) interconnects are introduced. The goal of this study is to reduce crosstalk without using additional PCB components in the design. Specifically, we use stepped impedance elements and open-circuited stubs of uniform length and width on the victim traces to suppress high-frequency electromagnetic interference and to equalize propagation delays or capacitive and inductive couplings between PCB traces. The overall design is very similar to the usual low-pass filter configurations, which are difficult to implement in the prototype testing. The proposed approach shows remarkably better results when compared with conventional intervening guard trace schemes. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.

Printed Circuit Board Assembly Optimization Based on Genetic Algorithm with Model Constraints of Polychromatic Sets

Aimed at the optimization problem of printed circuit board (PCB) assembly workshop (WPCBA) with multiple assembly machines and tasks, combined with polychromatic sets and genetic algorithm (GA), an optimization method is presented to optimize PCB assignment, component allocation and PCB assembly sequence problem simultaneously. On the basis of the polychromatic sets theory, numerical contour matrix is presented to describe the constraint of machine and operation sequence for WPCBA optimization problem and formulate the constraint model. Constraint model guarantees that GA searches optimal result in the effective solution space and simplify the calculation of fitness value. Moreover, if the machine and assembly task are changed, through a simple modification of constraint model, the WPCBA problem would be optimized conveniently. Computational results indicate that the solution efficiency of WPCBA optimization problem can be improved significantly and the dynamical optimization can be implemented.