Analysis of surface insulation resistance related failures in electronics by circuit simulation

Abstract

PurposeThe purpose of this study is to show that the humidity levels for surface insulation resistance (SIR)-related failures are dependent on the type of activators used in no-clean flux systems and to demonstrate the possibility of simulating the effects of humidity and contamination on printed circuit board components and sensitive parts if typical SIR data connected to a particular climatic condition are available. This is shown on representative components and typical circuits.Design/methodology/approachA range of SIR values obtained on SIR patterns with 1,476 squares was used as input data for the circuit analysis. The SIR data were compared to the surface resistance values observable on a real device printed circuit board assembly. SIR issues at the component and circuit levels were analysed on the basis of parasitic circuit effects owing to the formation of a water layer as an electrical conduction medium.FindingsThis paper provides a summary of the effects of contamination with various weak organic acids representing the active components in no-clean solder flux residue, and demonstrates the effect of humidity and contamination on the possible malfunctions and errors in electronic circuits. The effect of contamination and humidity is expressed as drift from the nominal resistance values of the resistors, self-discharge of the capacitors and the errors in the circuits due to parasitic leakage currents (reduction of SIR).Practical/implicationsThe methodology of the analysis of the circuits using a range of empirical leakage resistance values combined with the knowledge of the humidity and contamination profile of the electronics can be used for the robust design of a device, which is also important for electronic products relying on low current consumption for long battery lifetime.Originality/valueExamples provide a basic link between the combined effect of humidity and contamination and the performance of electronic circuits. The methodology shown provides the possibility of addressing the climatic reliability of an electronic device at the early stage of device design by using typical SIR data representing the possible climate exposure.