Complexity Of Integrated Circuits Research Articles

Optimizing Data Transfer Across Asynchronous Clock Domains: A Comprehensive Approach to Asynchronous FIFO Circuit Design

As integrated circuit (IC) design continues to advance in scale, there is a growing trend towards integrating more components onto the same IC board, resulting in larger circuit boards. These expanded circuit boards often encompass diverse asynchronous clock domains, leading to inevitable data transfer challenges between these distinct clock domains. This research article focuses on Verilog-based asynchronous first in first out (FIFO) design as a solution to effectively address this issue and offers a robust design approach to enhance circuit integration and stability. By employing conventional asynchronous FIFO design principles, such as the utilization of binary conversion Gray code to synchronize clock operations for pointer-to-address mapping and the incorporation of empty/full flag status bits to facilitate empty/full signal generation determination, seamless data transfer between various asynchronous clock domains is successfully achieved. Furthermore, this article includes comprehensive testing and simulation using Testbench to validate the asynchronous FIFO circuit, with successful results. The primary objective of this article is to present a well-established and comprehensive design methodology for asynchronous FIFO circuits, equipping designers with a mature and reliable approach to tackle the challenges posed by increasingly complex IC designs.

Quantitative Research on Generalized Linear Modeling of SEU and Test Programs Based on Small Sample Data

Complex integrated circuits (ICs) have complex functions and various working modes, which have many factors affecting the performance of a single event effect. The single event effect performance of complex ICs is highly program-dependent and the single event sensitivity of a typical operating mode is generally used to represent the single event performance of the circuits. Traditional evaluation methods fail to consider the cross effects of multiple factors and the comprehensive effects of each factor on the single event soft error cross section. In order to solve this problem, a new quantitative study method of single event error cross section based on a generalized linear model for different test programs is proposed. The laser test data is divided into two groups: a training set and a validation set. The former is used for model construction and parameter estimation based on five methods, such as the generalized linear model and Ensemble, while the latter is used for quantitative evaluation and validation of a single event soft error cross section of the model. In terms of percentage error, the minimum mean estimation error on the validation set is 13.93%. Therefore, it has a high accuracy to evaluate the single event soft error cross section of circuits under different testing programs based on the generalized linear model, which provides a new idea for the evaluation of a single event effect on complex ICs.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

2D semiconductors, such as molybdenum disulfide (MoS2 ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS2 film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS2 field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS2 logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

During development of power Integrated Circuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{4}$ </tex-math></inline-formula> -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions - the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time - and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

Heterogeneous Functional Dielectric Patterns for Charge-Carrier Modulation in Ultraflexible Organic Integrated Circuits.

Flexible electronics have gained considerable attention for application in wearable devices. Organic transistors are potential candidates to develop flexible integrated circuits (ICs). A primary technique for maximizing their reliability, gain, and operation speed is the modulation of charge-carrier behavior in the respective transistors fabricated on the same substrate. In this work, heterogeneous functional dielectric patterns (HFDP) of ultrathin polymer gate dielectrics of poly((±)endo,exo-bicyclo[2.2.1]hept-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) are introduced. The HFDP that are obtained via the photo-Fries rearrangement by ultraviolet radiation in the homogeneous PNDPE provide a functional area for charge-carrier modulation. This leads to programmable threshold voltage control over a wide range (-1.5 to +0.2V) in the transistors with a high patterning resolution, at 2V operational voltage. The transistors also exhibit high operational stability over 140 days and under the bias-stress duration of 1800s. With the HFDP, the performance metrics of ICs, for example, the noise margin and gain of the zero-VGS load inverters and the oscillation frequency of ring oscillators are improved to 80%, 1200, and 2.5kHz, respectively, which are the highest among the previously reported zero-VGS -based organic circuits. The HFDP can be applied to much complex and ultraflexible ICs.

Test yield and quality analysis models of chips

ABSTRACTIn this work, we utilized a digital integrated-circuit (IC) testing model (DITM), based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor products. A circuit or chip has multiple parameters and the relationships among these parameters at different levels are complicated. To simply express numerous and complex interrelated IC or chip manufacturing and testing parameters, we assumed a normal distribution of manufacturability and then standardized and related all other parameters. On applying the Digital integrated circuit testing model (DITM) to data on Accuracy Requirements in At-Speed Functional Test and International technology roadmap for semiconductors (ITRS Roadmap), the simulated results clearly indicated that when the threshold value of a quality control test is determined, the DITM can accurately and effectively predict future Yt (Test Yield).

Compact modelling and SPICE simulation for three-dimensional, inkjet-printed organic transistors, inverters and ring oscillators

We report an in-depth study of three-dimensional (3D) inkjet-printed flexible organic field-effect transistors (FETs) and integrated circuits (ICs), and demonstrate the necessity, the feasibility and the key aspects of modelling-driven design and analysis. In particular, we performed compact modelling of the flexible printed organic FETs to determine transistor parameters from measured electrical characteristics, and to optimize the design of transistors for a balanced inverter. We also conducted a SPICE simulation of both static and dynamic behaviours of flexible printed organic complementary inverters and ring oscillators. This study revealed design rules to guide fabrication of the 3D structure of the inverter. The study also showed that the parasitic capacitances are dominant factors that determine the transient behaviour of the ring oscillator. Our work provides insights that can guide further improvement of flexible printed organic FETs and ICs towards the realisation of increasingly complex organic ICs and unconventional electronic applications.

(Invited) 3D Monolithic Integration in Flexible Organic Printed Transistors

Despite the significant enhancements in material properties such as carrier mobility, few attempts have been made to print organic integrated circuits (ICs). The relatively large size of printed features (typically 10 μm – 100 μm) have limited the implementation of organic ICs with reasonable transistor densities. To overcome the limitation, we introduce three-dimensional (3D) integration of inkjet-printed organic transistors and circuits. We fabricated a p-type organic field-effect transistor that is inkjet-printed on top of an n-type organic field-effect transistor with a shared gate joining the two transistors. Based on the common-gate transistor-on-transistor structure, a complementary inverter array is fabricated with a high static noise margin and reliable characteristics. We have further developed 3D integration of a dual-gate NAND technology fabricated by printing technique with a demonstration of flexible logic circuits. The vertical stacking of independent-gate controlled dual gate transistors offers enhanced on-current, lowered sub-threshold swing, increased device stability and density. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs, and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices

Novel thermal model of microchannel cooling system designed for fast simulation of liquid-cooled ICs

The research and design of liquid-cooled integrated circuits (IC) relies heavily on accurate simulation. Ideally, finite-element-method (FEM) based tools should be used for this purpose. However, in most cases a fully coupled thermo-fluidic simulation of complex ICs is very long, mostly due to the fact that the simulation of fluid dynamics is very time consuming. Therefore, in this paper we propose a novel model for thermal simulation of ICs cooled by integrated microchannels which significantly reduces the simulation time. The new approach is based on removing the fluid from the model and treating the solid-liquid boundary as a convective boundary, described by the convection equation. It is shown that the proposed model offers very good accuracy in steady-state, with errors below 3 °C in every chip point. In transient domain the results are equally good, with the maximum error around 3.3 °C (6% relative error). Moreover, the simulation times have been reduced by about two orders of magnitude with respect to fully coupled FEM simulation. However, the proposed model has also important limitations: currently ICs with only one layer of straight microchannels are supported and the model requires recalculation if some chip parameters are changed.

(Invited) High-Performance Carbon Nanotube Based Flexible Electronics for Integrated Smart Sensor System

As the information processing part in flexible integrated sensor systems, there are several basic requirements for the integrated circuits (ICs) in addition to flexibility, including high speed, low power consumption, medium to large scale integration, etc. Currently there is no solution that can meets all the requirements. Here we present our recent progress in high-performance flexible thin film transistors based on carbon nanotube (CNT). The transistors exhibit large on-state current, high mobility (>80 cm2V-1s-1), small subthreshold slop (<70 mVdec-1), and large current on/off ratio (>105), all with an operating voltages of 2 V. The developed fabrication approach presents high yield and the transistors’ performances are highly uniform with well controlled threshold voltage distribution, which enable the realization of various logic gates and the most complex CNT-based ICs on flexible substrate. Finally, an integrated smart sensor system with in-situ signal processing capability for human body monitoring based on CNT was demonstrated.

Three-Dimensional, Inkjet-Printed Organic Transistors and Integrated Circuits with 100% Yield, High Uniformity, and Long-Term Stability.

In this paper, we demonstrate three-dimensional (3D) integrated circuits (ICs) based on a 3D complementary organic field-effect transistor (3D-COFET). The transistor-on-transistor structure was achieved by vertically stacking a p-type OFET over an n-type OFET with a shared gate joining the two transistors, effectively halving the footprint of printed transistors. All the functional layers including organic semiconductors, source/drain/gate electrodes, and interconnection paths were fully inkjet-printed except a parylene dielectric which was deposited by chemical vapor deposition. An array of printed 3D-COFETs and their inverter logic gates comprising over 100 transistors showed 100% yield, and the uniformity and long-term stability of the device were also investigated. A full-adder circuit, the most basic computing unit, has been successfully demonstrated using nine NAND gates based on the 3D structure. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs (increased transistor density, 100% yield, high uniformity, and long-term stability), and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices.

Reduction of EMC Emissions in Mixed Signal Integrated Circuits with Embedded LIN Driver

This paper describes several methods for reduction of electromagnetic emissions (EME) of mixed signal integrated circuits (IC). The focus is on the impact that a LIN bus communication block has on a complex IC which contains analog blocks, noisy digital block, microcore (μC) and several types of memories. It is used in an automotive environment, where EMC emission reduction is one of the key success factors. Several proposed methods for EME reduction are described and implemented on three test chips. These methods include current consumption reduction, internal on-chip decoupling, ground separation and different linear voltage regulator topologies. Measurement results of several fabricated test chips are shown and discussed.

Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps

Hardware Trojans are malicious alterations or injections of unwanted circuitry to integrated circuits (ICs) by untrustworthy factories. They render great threat to the security of modern ICs by various unwanted activities such as bypassing or disabling the security fence of a system, leaking confidential information, deranging, or destroying the entire chip. Traditional testing strategies are becoming ineffective since these techniques suffer from decreased sensitivity toward small Trojans because of oversized chip and large amount of process variation present in nanometer technologies. The production volume along with decreased controllability and observability to complex ICs internals make it difficult to efficiently perform Trojan detection using typical structural tests like path latency and leakage power. In this paper, we propose a completely new post-silicon multimodal approach using runtime thermal and power maps for Trojan detection and localization. Utilizing the novel framework, we propose two different Trojan detection methods involving 2-D principal component analysis. First, supervised thresholding in case training data set is available and second, unsupervised clustering which require no prior characterization data of the chip. We introduce 11 regularization in the thermal to power inversion procedure which improves Trojan detection accuracy. To characterize ICs accurately, we perform our experiments in presence of realistic CMOS process variation. Our experimental evaluations reveal that our proposed methodology can detect very small Trojans with 3-4 orders of magnitude smaller power consumptions than the total power usage of the chip, while it scales very well because of the spatial view to ICs internals by the thermal mapping.

Modularized construction of general integrated circuits on individual carbon nanotubes.

While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

New Combined Approach for the Evaluation of the Soft-Errors of Complex ICs

In this paper, we propose to investigate the relevance of a combined use of the methodologies commonly used to estimate the fault tolerance of complex integrated circuits (IC) towards radiation effects, in order to propose a clear procedure for estimating this sensitivity. As presented, each of the well-known methodologies is relevant to provide a particular type of result: the pulsed laser stimulation (PLS) to analyze the device memory layout as well as to validate the test set up thanks to fault injection, the accelerator test to evaluate the static soft-error rate (SER), and the Statistical Fault Injection (SFI) to determine the derating factor due to the circuit and the application. Nevertheless, taken separately, none of them is suitable to exhaustively assess the SER at application level in complex ICs. This paper presents an accurate methodology coupling those techniques applied on a STRATIX IV FPGA target with an embedded Nios II Soft-Core running different applications.

Thermal-aware DC IR-drop co-analysis using non-conformal domain decomposition methods

Almost all practical engineering applications are multi-physics in nature, and various physical phenomena usually interact and couple with each other. For instance, the resistivity of most conducting metals increases linearly with increases in the surrounding temperature resulting from Joule heating by electrical currents flowing through conductors. Therefore, in order to accurately characterize the performance of high-power integrated circuits (ICs), packages and printed circuit boards (PCBs), it is essential to account for both electrical and thermal effects and the intimate couplings between them. In this paper, we present non-conformal, non-overlapping domain decomposition methods (DDMs) for thermal-aware direct current (DC) IR drop co-analysis of high-power chip-package-PCBs. Here, IR stands for the finite resistivity (R) of metals and current (I) drawn off from the power/ground planes. The proposed DDM starts by partitioning the composite device into inhomogeneous sub-regions with temperature-dependent material properties. Subsequently, each sub-domain is meshed independently according to its own characteristic features. As a consequence, the troublesome mesh-generation task for complex ICs can be greatly subdued. The proposed thermal-aware DC IR drop co-analysis applies the non-conformal DDM for both conduction and steady-state heat-transfer analyses with a two-way coupling between them. Numerical examples, including an IC package and a chip-package-PCB, demonstrate the flexibility and potential of the proposed thermal-aware DC IR-drop co-analysis using non-conformal DDMs.

Quantitatively analyzing the performance of integrated circuits and their reliability

Testing, instrumentation, and measurement electronics require high reliability and high quality complex integrated circuits (ICs) to ensure the accuracy of the analytical data they process. Microprocessors and other complex ICs such as FPGAs are considered the most important components within instrumentation. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit board, and due to their complexity and roles within a circuit, performance-based failure can be considered an even larger concern. Stability of device parameters is key to guaranteeing that a system will function according to its design. We discuss the importance of microprocessor and IC device reliability and how modifying the operational parameters of these devices through over- and under-clocking can either reduce or improve overall reliability, respectively, and directly affect the lifetime of the system in which these devices are installed.

Development of Compact Models for Electronics Cooling: Using the Multigrid Operator to Generate Reduced-Order Description of Devices

The need for compact models for ICs is a well-recognized problem in electronics cooling simulations of systems containing multiple PCBs and many devices per board. The disparate length scales inherent in the problem and the necessity of resolving these size scales render the computational problem intractable. Many resistance-capacitance (RC) network compact models have been proposed in the literature. We present a methodology to automatically construct both the topology and characteristics of the reduced-order or compact models of devices [primarily Integrated Circuit (IC) packages] for use in system-level simulations using the multigrid operator. The multigrid technique has been extensively used over the past 20 years to accelerate the solution of linear systems. In addition to automatically generating both the RC network topology and its values, the procedure is general enough to be applicable for complex IC device types (such as multichip modules), stack-up dies, distributed sources on the die, DC-DC converters, and devices such as hard disk drives.

Direct Imaging of Device Characteristics In a Focused ion Beam System

Abstract A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

Mixed microprocessor-random logic approach for innovative pacing systems.

Modern pacing systems are becoming more and more sophisticated. Conversion of the information supplied by a sensor into suitable parameters for a rate controlling algorithm and the management of complex timing are common tasks for an integrated circuit (IC) in cardiac pacing. An effective solution consists of using a microprocessor to implement algorithms and pacing modes in a flexible way. The key point of using the same hardware resources for different tasks on a time sharing basis allows the design of a less complex IC when compared to a random logic structure with the same performances. The major design problems in a full microprocessor solution are its relatively low operating speed due to the low frequency clock necessary for low current drain, and the sequential structure of the machine itself. This can lead to unacceptable timing inaccuracy in all situations requiring the management of complex decision trees. In order to take full benefit from the advantages of a microprocessor structure without these drawbacks, a mixed microprocessor-random logic approach has been investigated. This architecture uses a microprocessor core to perform all high level nonreal-time operations (setup of the pacing cycle, data reduction and processing, data integrity checks) while a set of random logic peripherals is used for all critical timing aspects.